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https://github.com/brain-hackers/u-boot-brain
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MEM_H_
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#define _MEM_H_
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/*
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* GPMC settings -
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* Definitions is as per the following format
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* #define <PART>_GPMC_CONFIG<x> <value>
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* Where:
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* PART is the part name e.g. STNOR - Intel Strata Flash
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* x is GPMC config registers from 1 to 6 (there will be 6 macros)
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* Value is corresponding value
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*
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* For every valid PRCM configuration there should be only one definition of
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* the same. if values are independent of the board, this definition will be
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* present in this file if values are dependent on the board, then this should
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* go into corresponding mem-boardName.h file
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*
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* Currently valid part Names are (PART):
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* M_NAND - Micron NAND
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*/
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#define GPMC_SIZE_256M 0x0
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#define GPMC_SIZE_128M 0x8
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#define GPMC_SIZE_64M 0xC
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#define GPMC_SIZE_32M 0xE
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#define GPMC_SIZE_16M 0xF
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#define M_NAND_GPMC_CONFIG1 0x00000800
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#define M_NAND_GPMC_CONFIG2 0x001e1e00
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#define M_NAND_GPMC_CONFIG3 0x001e1e00
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#define M_NAND_GPMC_CONFIG4 0x16051807
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#define M_NAND_GPMC_CONFIG5 0x00151e1e
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#define M_NAND_GPMC_CONFIG6 0x16000f80
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#define M_NAND_GPMC_CONFIG7 0x00000008
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/* max number of GPMC Chip Selects */
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#define GPMC_MAX_CS 8
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/* max number of GPMC regs */
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#define GPMC_MAX_REG 7
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#define PISMO1_NOR 1
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#define PISMO1_NAND 2
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#define PISMO2_CS0 3
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#define PISMO2_CS1 4
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#define PISMO1_ONENAND 5
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#define DBG_MPDB 6
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#define PISMO2_NAND_CS0 7
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#define PISMO2_NAND_CS1 8
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/* make it readable for the gpmc_init */
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#define PISMO1_NOR_BASE FLASH_BASE
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#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
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#define PISMO1_NAND_SIZE GPMC_SIZE_256M
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#endif /* endif _MEM_H_ */
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