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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
218 lines
4.4 KiB
C
218 lines
4.4 KiB
C
/*
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* (C) Copyright 2000-2009
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* Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
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* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/spr_misc.h>
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#include <asm/arch/spr_defs.h>
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static void sel_1v8(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 ddr1v8, ddr2v5;
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
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ddr2v5 &= 0x8080ffc0;
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ddr2v5 |= 0x78000003;
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writel(ddr2v5, &misc_p->ddr_2v5_compensation);
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
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ddr1v8 &= 0x8080ffc0;
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ddr1v8 |= 0x78000010;
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writel(ddr1v8, &misc_p->ddr_1v8_compensation);
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while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
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;
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}
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static void sel_2v5(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 ddr1v8, ddr2v5;
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
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ddr1v8 &= 0x8080ffc0;
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ddr1v8 |= 0x78000003;
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writel(ddr1v8, &misc_p->ddr_1v8_compensation);
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
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ddr2v5 &= 0x8080ffc0;
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ddr2v5 |= 0x78000010;
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writel(ddr2v5, &misc_p->ddr_2v5_compensation);
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while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
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;
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}
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/*
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* plat_ddr_init:
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*/
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void plat_ddr_init(void)
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{
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 ddrpad;
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u32 core3v3, ddr1v8, ddr2v5;
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/* DDR pad register configurations */
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ddrpad = readl(&misc_p->ddr_pad);
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ddrpad &= ~DDR_PAD_CNF_MSK;
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#if (CONFIG_DDR_HCLK)
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ddrpad |= 0xEAAB;
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#elif (CONFIG_DDR_2HCLK)
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ddrpad |= 0xEAAD;
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#elif (CONFIG_DDR_PLL2)
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ddrpad |= 0xEAAD;
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#endif
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writel(ddrpad, &misc_p->ddr_pad);
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/* Compensation register configurations */
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core3v3 = readl(&misc_p->core_3v3_compensation);
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core3v3 &= 0x8080ffe0;
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core3v3 |= 0x78000002;
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writel(core3v3, &misc_p->core_3v3_compensation);
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
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ddr1v8 &= 0x8080ffc0;
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ddr1v8 |= 0x78000004;
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writel(ddr1v8, &misc_p->ddr_1v8_compensation);
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
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ddr2v5 &= 0x8080ffc0;
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ddr2v5 |= 0x78000004;
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writel(ddr2v5, &misc_p->ddr_2v5_compensation);
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if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
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/* Software memory configuration */
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if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
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sel_1v8();
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else
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sel_2v5();
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} else {
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/* Hardware memory configuration */
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if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
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sel_1v8();
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else
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sel_2v5();
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}
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}
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/*
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* soc_init:
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*/
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void soc_init(void)
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{
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/* Nothing to be done for SPEAr600 */
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}
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/*
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* xxx_boot_selected:
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*
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* return true if the particular booting option is selected
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* return false otherwise
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*/
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static u32 read_bootstrap(void)
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{
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return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
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& CONFIG_SPEAR_BOOTSTRAPMASK;
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}
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int snor_boot_selected(void)
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{
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u32 bootstrap = read_bootstrap();
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if (SNOR_BOOT_SUPPORTED) {
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/* Check whether SNOR boot is selected */
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if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
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CONFIG_SPEAR_ONLYSNORBOOT)
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return true;
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
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CONFIG_SPEAR_NORNAND8BOOT)
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return true;
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
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CONFIG_SPEAR_NORNAND16BOOT)
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return true;
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}
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return false;
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}
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int nand_boot_selected(void)
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{
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u32 bootstrap = read_bootstrap();
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if (NAND_BOOT_SUPPORTED) {
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/* Check whether NAND boot is selected */
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
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CONFIG_SPEAR_NORNAND8BOOT)
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return true;
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
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CONFIG_SPEAR_NORNAND16BOOT)
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return true;
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}
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return false;
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}
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int pnor_boot_selected(void)
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{
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/* Parallel NOR boot is not selected in any SPEAr600 revision */
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return false;
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}
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int usb_boot_selected(void)
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{
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u32 bootstrap = read_bootstrap();
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if (USB_BOOT_SUPPORTED) {
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/* Check whether USB boot is selected */
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if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
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return true;
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}
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return false;
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}
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int tftp_boot_selected(void)
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{
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/* TFTP boot is not selected in any SPEAr600 revision */
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return false;
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}
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int uart_boot_selected(void)
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{
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/* UART boot is not selected in any SPEAr600 revision */
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return false;
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}
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int spi_boot_selected(void)
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{
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/* SPI boot is not selected in any SPEAr600 revision */
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return false;
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}
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int i2c_boot_selected(void)
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{
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/* I2C boot is not selected in any SPEAr600 revision */
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return false;
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}
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int mmc_boot_selected(void)
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{
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return false;
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}
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void plat_late_init(void)
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{
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spear_late_init();
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}
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