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https://github.com/brain-hackers/u-boot-brain
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![Prabhakar Kushwaha](/assets/img/avatar_default.png)
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
205 lines
5.1 KiB
C
205 lines
5.1 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <phy.h>
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch/fdt.h>
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#endif
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
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{
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return fdt_setprop_string(blob, offset, "phy-connection-type",
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phy_string_for_interface(phyc));
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}
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#ifdef CONFIG_MP
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void ft_fixup_cpu(void *blob)
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{
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int off;
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__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
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fdt32_t *reg;
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int addr_cells;
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u64 val, core_id;
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size_t *boot_code_size = &(__secondary_boot_code_size);
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off = fdt_path_offset(blob, "/cpus");
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if (off < 0) {
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puts("couldn't find /cpus node\n");
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return;
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}
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of_bus_default_count_cells(blob, off, &addr_cells, NULL);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
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if (reg) {
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core_id = of_read_number(reg, addr_cells);
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if (core_id == 0 || (is_core_online(core_id))) {
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val = spin_tbl_addr;
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val += id_to_core(core_id) *
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SPIN_TABLE_ELEM_SIZE;
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val = cpu_to_fdt64(val);
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fdt_setprop_string(blob, off, "enable-method",
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"spin-table");
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fdt_setprop(blob, off, "cpu-release-addr",
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&val, sizeof(val));
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} else {
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debug("skipping offline core\n");
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}
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} else {
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puts("Warning: found cpu node without reg property\n");
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}
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off = fdt_node_offset_by_prop_value(blob, off, "device_type",
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"cpu", 4);
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}
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fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
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*boot_code_size);
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}
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#endif
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/*
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* the burden is on the the caller to not request a count
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* exceeding the bounds of the stream_ids[] array
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*/
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void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt)
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{
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int i;
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if (count > max_cnt) {
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printf("\n%s: ERROR: max per-device stream ID count exceed\n",
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__func__);
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return;
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}
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for (i = 0; i < count; i++)
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stream_ids[i] = start_id++;
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}
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/*
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* This function updates the mmu-masters property on the SMMU
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* node as per the SMMU binding-- phandle and list of stream IDs
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* for each MMU master.
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*/
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void append_mmu_masters(void *blob, const char *smmu_path,
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const char *master_name, u32 *stream_ids, int count)
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{
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u32 phandle;
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int smmu_nodeoffset;
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int master_nodeoffset;
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int i;
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/* get phandle of mmu master device */
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master_nodeoffset = fdt_path_offset(blob, master_name);
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if (master_nodeoffset < 0) {
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printf("\n%s: ERROR: master not found\n", __func__);
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return;
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}
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phandle = fdt_get_phandle(blob, master_nodeoffset);
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if (!phandle) { /* if master has no phandle, create one */
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phandle = fdt_create_phandle(blob, master_nodeoffset);
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if (!phandle) {
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printf("\n%s: ERROR: unable to create phandle\n",
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__func__);
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return;
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}
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}
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/* append it to mmu-masters */
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smmu_nodeoffset = fdt_path_offset(blob, smmu_path);
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if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
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phandle) < 0) {
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printf("\n%s: ERROR: unable to update SMMU node\n", __func__);
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return;
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}
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/* for each stream ID, append to mmu-masters */
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for (i = 0; i < count; i++) {
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fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
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stream_ids[i]);
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}
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/* fix up #stream-id-cells with stream ID count */
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if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells",
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count) < 0)
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printf("\n%s: ERROR: unable to update #stream-id-cells\n",
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__func__);
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}
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/*
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* The info below summarizes how streamID partitioning works
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* for ls2080a and how it is conveyed to the OS via the device tree.
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*
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* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
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* -all legacy devices get a unique ICID assigned and programmed in
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* their AMQR registers by u-boot
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* -u-boot updates the hardware device tree with streamID properties
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* for each platform/legacy device (smmu-masters property)
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*
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* -PCIe
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* -for each PCI controller that is active (as per RCW settings),
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* u-boot will allocate a range of ICID and convey that to Linux via
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* the device tree (smmu-masters property)
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*
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* -DPAA2
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* -u-boot will allocate a range of ICIDs to be used by the Management
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* Complex for containers and will set these values in the MC DPC image.
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* -the MC is responsible for allocating and setting up ICIDs
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* for all DPAA2 devices.
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*
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*/
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#ifdef CONFIG_FSL_LSCH3
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static void fdt_fixup_smmu(void *blob)
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{
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int nodeoffset;
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nodeoffset = fdt_path_offset(blob, "/iommu@5000000");
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if (nodeoffset < 0) {
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printf("\n%s: WARNING: no SMMU node found\n", __func__);
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return;
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}
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/* fixup for all PCI controllers */
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#ifdef CONFIG_PCI
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fdt_fixup_smmu_pcie(blob);
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#endif
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}
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#endif
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_MP
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ft_fixup_cpu(blob);
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#endif
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#ifdef CONFIG_SYS_NS16550
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do_fixup_by_compat_u32(blob, "fsl,ns16550",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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#ifdef CONFIG_FSL_ESDHC
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fdt_fixup_esdhc(blob, bd);
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#endif
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#ifdef CONFIG_FSL_LSCH3
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fdt_fixup_smmu(blob);
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#endif
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}
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