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Kim Phillips 1a2e203b31 mpc83xx: turn on icache in core initialization to improve u-boot boot time 
before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:44:56 -05:00
..
arm arm: Move cpu/$CPU to arch/arm/cpu/$CPU 2010-04-13 09:13:24 +02:00
avr32 avr32: Move cpu/at32ap/* to arch/avr32/cpu/* 2010-04-13 09:13:25 +02:00
blackfin blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/* 2010-04-13 09:13:25 +02:00
i386 i386: Move cpu/i386/* to arch/i386/cpu/* 2010-04-13 09:13:26 +02:00
m68k m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU 2010-04-13 09:13:24 +02:00
microblaze microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/* 2010-04-13 09:13:26 +02:00
mips mips: Move cpu/mips/* to arch/mips/cpu/* 2010-04-13 09:13:25 +02:00
nios nios: Move cpu/nios/* to arch/nios/cpu/* 2010-04-13 09:13:27 +02:00
nios2 nios2: Move individual board linker scripts to common script in cpu tree. 2010-04-16 16:12:39 -04:00
powerpc mpc83xx: turn on icache in core initialization to improve u-boot boot time 2010-04-22 18:44:56 -05:00
sh sh: Move cpu/$CPU to arch/sh/cpu/$CPU 2010-04-13 09:13:17 +02:00
sparc sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23] 2010-04-13 09:13:26 +02:00