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https://github.com/brain-hackers/u-boot-brain
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154b5484ac
Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* -----------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/hardware.h>
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#include "../common/misc.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SONATA;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Configure AEMIF pins (although this should be configured at boot time
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* with pull-up/pull-down resistors) */
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REG(PINMUX0) = 0x00000c1f;
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davinci_errata_workarounds();
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_GPIO);
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#if !defined(CONFIG_SYS_USE_DSPLINK)
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/* Powerup the DSP */
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dsp_on();
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#endif /* CONFIG_SYS_USE_DSPLINK */
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davinci_enable_uart0();
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davinci_enable_emac();
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davinci_enable_i2c();
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lpsc_on(DAVINCI_LPSC_TIMER1);
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timer_init();
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return(0);
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}
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int misc_init_r(void)
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{
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uint8_t eeprom_enetaddr[6];
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/* Read Ethernet MAC address from EEPROM if available. */
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if (dvevm_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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return(0);
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}
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#ifdef CONFIG_NAND_DAVINCI
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/* Set WP on deselect, write enable on select */
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static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
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{
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#define GPIO_SET_DATA01 0x01c67018
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#define GPIO_CLR_DATA01 0x01c6701c
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#define GPIO_NAND_WP (1 << 4)
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#ifdef SONATA_BOARD_GPIOWP
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if (chip < 0) {
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REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
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} else {
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REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
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}
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#endif
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}
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int board_nand_init(struct nand_chip *nand)
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{
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davinci_nand_init(nand);
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nand->select_chip = nand_sonata_select_chip;
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return 0;
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}
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#endif /* CONFIG_NAND_DAVINCI */
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