mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 21:09:00 +09:00
187 lines
4.9 KiB
C
187 lines
4.9 KiB
C
/*
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Low Power Divider specifications
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*/
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#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
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#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
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#define CLOCK_PLL_FVCO_MAX 540000000
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#define CLOCK_PLL_FVCO_MIN 300000000
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#define CLOCK_PLL_FSYS_MAX 266666666
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#define CLOCK_PLL_FSYS_MIN 100000000
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#define MHZ 1000000
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void clock_enter_limp(int lpdiv)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
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int i, j;
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/* Check bounds of divider */
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if (lpdiv < CLOCK_LPD_MIN)
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lpdiv = CLOCK_LPD_MIN;
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if (lpdiv > CLOCK_LPD_MAX)
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lpdiv = CLOCK_LPD_MAX;
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/* Round divider down to nearest power of two */
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for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
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/* Apply the divider to the system clock */
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ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
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/* Enable Limp Mode */
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ccm->misccr |= CCM_MISCCR_LIMP;
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}
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/*
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* brief Exit Limp mode
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* warning The PLL should be set and locked prior to exiting Limp mode
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*/
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void clock_exit_limp(void)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
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volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
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/* Exit Limp mode */
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ccm->misccr &= ~CCM_MISCCR_LIMP;
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/* Wait for the PLL to lock */
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while (!(pll->psr & PLL_PSR_LOCK)) ;
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}
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/*
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* get_clocks() fills in gd->cpu_clock and gd->bus_clk
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*/
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int get_clocks(void)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
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volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
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volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
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volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
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int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
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int pllmult_pci[] = { 12, 6, 16, 8 };
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int vco, bPci, temp, fbtemp, pcrvalue;
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int *pPllmult = NULL;
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u16 fbpll_mask;
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u8 cpldmode;
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/* To determine PCI is present or not */
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if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
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((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
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pPllmult = &pllmult_pci[0];
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fbpll_mask = 3;
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bPci = 1;
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} else {
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pPllmult = &pllmult_nopci[0];
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fbpll_mask = 7;
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#ifdef CONFIG_PCI
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gd->pci_clk = 0;
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#endif
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bPci = 0;
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}
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#ifdef CONFIG_M54455EVB
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/* Temporary place here, belongs in board/freescale/... */
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/* Temporary read from CCR- fixed fb issue, must be the same clock
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as pci or input clock, causing cpld/fpga read inconsistancy */
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fbtemp = pPllmult[ccm->ccr & fbpll_mask];
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/* Break down into small pieces, code still in flex bus */
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pcrvalue = pll->pcr & 0xFFFFF0FF;
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temp = fbtemp - 1;
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pcrvalue |= PLL_PCR_OUTDIV3(temp);
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pll->pcr = pcrvalue;
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cpldmode = *cpld & 0x03;
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if (cpldmode == 0) {
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/* RCON mode */
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vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
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if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
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/* invaild range, re-set in PCR */
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int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
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int i, j, bus;
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j = (pll->pcr & 0xFF000000) >> 24;
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for (i = j; i < 0xFF; i++) {
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vco = i * CFG_INPUT_CLKSRC;
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if (vco >= CLOCK_PLL_FVCO_MIN) {
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bus = vco / temp;
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if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
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continue;
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else
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break;
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}
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}
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pcrvalue = pll->pcr & 0x00FF00FF;
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fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
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pcrvalue |= ((i << 24) | fbtemp);
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pll->pcr = pcrvalue;
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}
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gd->vco_clk = vco; /* Vco clock */
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} else if (cpldmode == 2) {
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/* Normal mode */
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vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
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gd->vco_clk = vco; /* Vco clock */
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} else if (cpldmode == 3) {
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/* serial mode */
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}
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#endif /* CONFIG_M54455EVB */
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if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
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/* Limp mode */
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} else {
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gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
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temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
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gd->cpu_clk = vco / temp; /* cpu clock */
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temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
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gd->bus_clk = vco / temp; /* bus clock */
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temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
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gd->flb_clk = vco / temp; /* FlexBus clock */
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#ifdef CONFIG_PCI
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if (bPci) {
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temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
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gd->pci_clk = vco / temp; /* PCI clock */
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}
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#endif
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}
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return (0);
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}
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