mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1a048cd656
Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. to handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <exports.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FSL_MC_ENET)
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int i, interface;
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struct memac_mdio_info mdio_info;
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struct mii_dev *dev;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct memac_mdio_controller *reg;
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u32 srds_s1, cfg;
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cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
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FSL_CHASSIS3_SRDS1_PRTCL_MASK;
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cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
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srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
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/* Register the EMI 1 */
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fm_memac_mdio_init(bis, &mdio_info);
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
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/* Register the EMI 2 */
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fm_memac_mdio_init(bis, &mdio_info);
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switch (srds_s1) {
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case 0x1D:
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/*
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* XFI does not need a PHY to work, but to avoid U-boot use
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* default PHY address which is zero to a MAC when it found
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* a MAC has no PHY address, we give a PHY address to XFI
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* MAC error.
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*/
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wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
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wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
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wriop_set_phy_address(WRIOP1_DPMAC10, 0,
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QSGMII2_PORT4_PHY_ADDR);
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break;
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default:
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printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
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srds_s1);
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break;
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}
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for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
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interface = wriop_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_QSGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
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wriop_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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wriop_set_mdio(WRIOP1_DPMAC2, dev);
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cpu_eth_init(bis);
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#endif /* CONFIG_FMAN_ENET */
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_RESET_PHY_R)
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void reset_phy(void)
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{
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mc_env_boot();
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}
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#endif /* CONFIG_RESET_PHY_R */
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