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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Kunihiko Hayashi](/assets/img/avatar_default.png)
Add SPI controller driver implemented in Socionext UniPhier SoCs. This controller has the SPI master mode only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
414 lines
10 KiB
C
414 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* uniphier_spi.c - Socionext UniPhier SPI driver
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* Copyright 2019 Socionext, Inc.
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <spi.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SSI_CTL 0x00
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#define SSI_CTL_EN BIT(0)
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#define SSI_CKS 0x04
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#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
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#define SSI_CKS_CKPHS BIT(14)
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#define SSI_CKS_CKINIT BIT(13)
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#define SSI_CKS_CKDLY BIT(12)
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#define SSI_TXWDS 0x08
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#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
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#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
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#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_RXWDS 0x0c
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#define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
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#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_FPS 0x10
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#define SSI_FPS_FSPOL BIT(15)
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#define SSI_FPS_FSTRT BIT(14)
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#define SSI_SR 0x14
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#define SSI_SR_BUSY BIT(7)
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#define SSI_SR_TNF BIT(5)
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#define SSI_SR_RNE BIT(0)
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#define SSI_IE 0x18
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#define SSI_IC 0x1c
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#define SSI_IC_TCIC BIT(4)
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#define SSI_IC_RCIC BIT(3)
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#define SSI_IC_RORIC BIT(0)
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#define SSI_FC 0x20
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#define SSI_FC_TXFFL BIT(12)
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#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
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#define SSI_FC_RXFFL BIT(4)
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#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
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#define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
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#define SSI_FIFO_DEPTH 8U
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#define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
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#define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
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#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
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struct uniphier_spi_platdata {
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void __iomem *base;
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u32 frequency; /* input frequency */
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u32 speed_hz;
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uint deactivate_delay_us; /* Delay to wait after deactivate */
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uint activate_delay_us; /* Delay to wait after activate */
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};
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struct uniphier_spi_priv {
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void __iomem *base;
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u8 mode;
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u8 fifo_depth;
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u8 bits_per_word;
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ulong last_transaction_us; /* Time of last transaction end */
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};
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static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
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{
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u32 val;
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val = readl(priv->base + SSI_CTL);
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if (enable)
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val |= SSI_CTL_EN;
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else
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val &= ~SSI_CTL_EN;
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writel(val, priv->base + SSI_CTL);
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}
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static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
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{
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pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
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pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
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pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
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pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
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pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
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pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
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pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
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pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
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pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
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pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
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}
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct uniphier_spi_platdata *plat = bus->platdata;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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ulong delay_us; /* The delay completed so far */
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u32 val;
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/* If it's too soon to do another transaction, wait */
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if (plat->deactivate_delay_us && priv->last_transaction_us) {
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < plat->deactivate_delay_us)
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udelay(plat->deactivate_delay_us - delay_us);
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}
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val = readl(priv->base + SSI_FPS);
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if (priv->mode & SPI_CS_HIGH)
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val |= SSI_FPS_FSPOL;
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else
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val &= ~SSI_FPS_FSPOL;
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writel(val, priv->base + SSI_FPS);
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if (plat->activate_delay_us)
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udelay(plat->activate_delay_us);
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}
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct uniphier_spi_platdata *plat = bus->platdata;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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u32 val;
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val = readl(priv->base + SSI_FPS);
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if (priv->mode & SPI_CS_HIGH)
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val &= ~SSI_FPS_FSPOL;
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else
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val |= SSI_FPS_FSPOL;
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writel(val, priv->base + SSI_FPS);
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/* Remember time of this transaction so we can honour the bus delay */
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if (plat->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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}
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static int uniphier_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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u32 val, size;
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uniphier_spi_enable(priv, false);
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/* disable interrupts */
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writel(0, priv->base + SSI_IE);
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/* bits_per_word */
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size = priv->bits_per_word;
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val = readl(priv->base + SSI_TXWDS);
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val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
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val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
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val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_TXWDS);
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val = readl(priv->base + SSI_RXWDS);
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val &= ~SSI_RXWDS_DTLEN_MASK;
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val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_RXWDS);
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/* reset FIFOs */
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val = SSI_FC_TXFFL | SSI_FC_RXFFL;
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writel(val, priv->base + SSI_FC);
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/* FIFO threthold */
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val = readl(priv->base + SSI_FC);
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val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
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val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
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val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
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writel(val, priv->base + SSI_FC);
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/* clear interrupts */
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writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
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priv->base + SSI_IC);
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uniphier_spi_enable(priv, true);
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return 0;
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}
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static int uniphier_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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uniphier_spi_enable(priv, false);
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return 0;
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}
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static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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const u8 *tx_buf = dout;
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u8 *rx_buf = din, buf;
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u32 len = bitlen / 8;
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u32 tx_len, rx_len;
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u32 ts, status;
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int ret = 0;
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if (bitlen % 8) {
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dev_err(dev, "Non byte aligned SPI transfer\n");
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return -EINVAL;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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uniphier_spi_enable(priv, true);
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ts = get_timer(0);
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tx_len = len;
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rx_len = len;
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uniphier_spi_regdump(priv);
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while (tx_len || rx_len) {
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ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
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SSI_REG_TIMEOUT * 1000, false);
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if (ret) {
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if (ret == -ETIMEDOUT)
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dev_err(dev, "access timeout\n");
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break;
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}
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status = readl(priv->base + SSI_SR);
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/* write the data into TX */
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if (tx_len && (status & SSI_SR_TNF)) {
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buf = tx_buf ? *tx_buf++ : 0;
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writel(buf, priv->base + SSI_XDR);
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tx_len--;
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}
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/* read the data from RX */
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if (rx_len && (status & SSI_SR_RNE)) {
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buf = readl(priv->base + SSI_XDR);
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if (rx_buf)
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*rx_buf++ = buf;
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rx_len--;
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}
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if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
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dev_err(dev, "transfer timeout\n");
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ret = -ETIMEDOUT;
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break;
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}
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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uniphier_spi_enable(priv, false);
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return ret;
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}
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static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct uniphier_spi_platdata *plat = bus->platdata;
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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u32 val, ckdiv;
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if (speed > plat->frequency)
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speed = plat->frequency;
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/* baudrate */
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ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
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ckdiv = round_up(ckdiv, 2);
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val = readl(priv->base + SSI_CKS);
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val &= ~SSI_CKS_CKRAT_MASK;
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val |= ckdiv & SSI_CKS_CKRAT_MASK;
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writel(val, priv->base + SSI_CKS);
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return 0;
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}
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static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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u32 val1, val2;
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/*
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* clock setting
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* CKPHS capture timing. 0:rising edge, 1:falling edge
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* CKINIT clock initial level. 0:low, 1:high
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* CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
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* (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
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*
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* frame setting
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* FSPOL frame signal porarity. 0: low, 1: high
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* FSTRT start frame timing
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* 0: rising edge of clock, 1: falling edge of clock
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*/
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val1 = readl(priv->base + SSI_CKS);
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val2 = readl(priv->base + SSI_FPS);
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switch (mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
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val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
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val1 &= ~SSI_CKS_CKINIT;
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val2 &= ~SSI_FPS_FSTRT;
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break;
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case SPI_MODE_1:
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/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
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val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
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val2 |= SSI_FPS_FSTRT;
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break;
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case SPI_MODE_2:
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/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
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val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
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val1 &= ~SSI_CKS_CKPHS;
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val2 |= SSI_FPS_FSTRT;
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break;
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case SPI_MODE_3:
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/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
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val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
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val1 &= ~SSI_CKS_CKDLY;
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val2 &= ~SSI_FPS_FSTRT;
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break;
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}
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writel(val1, priv->base + SSI_CKS);
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writel(val2, priv->base + SSI_FPS);
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/* format */
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val1 = readl(priv->base + SSI_TXWDS);
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val2 = readl(priv->base + SSI_RXWDS);
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if (mode & SPI_LSB_FIRST) {
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val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
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val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
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}
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writel(val1, priv->base + SSI_TXWDS);
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writel(val2, priv->base + SSI_RXWDS);
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priv->mode = mode;
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return 0;
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}
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static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct uniphier_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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plat->base = devfdt_get_addr_ptr(bus);
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plat->frequency =
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fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
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plat->deactivate_delay_us =
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fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
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plat->activate_delay_us =
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fdtdec_get_int(blob, node, "spi-activate-delay", 0);
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plat->speed_hz = plat->frequency / 2;
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return 0;
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}
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static int uniphier_spi_probe(struct udevice *bus)
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{
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struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
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struct uniphier_spi_priv *priv = dev_get_priv(bus);
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priv->base = plat->base;
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priv->fifo_depth = SSI_FIFO_DEPTH;
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priv->bits_per_word = 8;
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return 0;
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}
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static const struct dm_spi_ops uniphier_spi_ops = {
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.claim_bus = uniphier_spi_claim_bus,
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.release_bus = uniphier_spi_release_bus,
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.xfer = uniphier_spi_xfer,
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.set_speed = uniphier_spi_set_speed,
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.set_mode = uniphier_spi_set_mode,
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};
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static const struct udevice_id uniphier_spi_ids[] = {
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{ .compatible = "socionext,uniphier-scssi" },
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{ /* Sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_spi) = {
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.name = "uniphier_spi",
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.id = UCLASS_SPI,
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.of_match = uniphier_spi_ids,
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.ops = &uniphier_spi_ops,
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.ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
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.probe = uniphier_spi_probe,
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};
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