mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
31d8267224
Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
329 lines
9.3 KiB
C
329 lines
9.3 KiB
C
/*
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* (C) Copyright 2004
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* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8220 1
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#define CONFIG_YUKON8220 1 /* ... on Yukon board */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
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determine the CPU speed. */
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#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
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#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Serial console configuration
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*/
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/* Define this for PSC console
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#define CONFIG_PSC_CONSOLE 1
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*/
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#define CONFIG_EXTUART_CONSOLE 1
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#ifdef CONFIG_EXTUART_CONSOLE
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# define CONFIG_CONS_INDEX 1
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# define CFG_NS16550_SERIAL
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# define CFG_NS16550
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# define CFG_NS16550_REG_SIZE 1
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# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
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# define CFG_NS16550_CLK 18432000
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#endif
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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#define CONFIG_NET_MULTI
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#define CONFIG_MII
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
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#define CONFIG_IPADDR 192.162.1.2
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.162.1.1
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#define CONFIG_GATEWAYIP 192.162.1.1
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#define CONFIG_HOSTNAME yukon
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1
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#define CFG_I2C_MODULE 1
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
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/*
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0
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#define CFG_ENV_SIZE 256
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*/
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/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
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else undefined it will boot from Intel Strata flash */
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#define CFG_AMD_BOOT 1
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/*
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* Flexbus Chipselect configuration
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*/
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#if defined (CFG_AMD_BOOT)
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#define CFG_CS0_BASE 0xfff0
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#define CFG_CS0_MASK 0x00080000 /* 512 KB */
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#define CFG_CS0_CTRL 0x003f0d40
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#define CFG_CS1_BASE 0xfe00
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#define CFG_CS1_MASK 0x01000000 /* 16 MB */
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#define CFG_CS1_CTRL 0x003f1540
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#else
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#define CFG_CS0_BASE 0xff00
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#define CFG_CS0_MASK 0x01000000 /* 16 MB */
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#define CFG_CS0_CTRL 0x003f1540
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#define CFG_CS1_BASE 0xfe08
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#define CFG_CS1_MASK 0x00080000 /* 512 KB */
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#define CFG_CS1_CTRL 0x003f0d40
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#endif
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#define CFG_CS2_BASE 0xf100
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#define CFG_CS2_MASK 0x00040000
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#define CFG_CS2_CTRL 0x003f1140
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#define CFG_CS3_BASE 0xf200
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#define CFG_CS3_MASK 0x00040000
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#define CFG_CS3_CTRL 0x003f1100
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#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
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#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
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#if defined (CFG_AMD_BOOT)
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#define CFG_AMD_BASE CFG_FLASH0_BASE
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#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
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#define CFG_FLASH_BASE CFG_AMD_BASE
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#else
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#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
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#define CFG_AMD_BASE CFG_FLASH1_BASE
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#define CFG_FLASH_BASE CFG_INTEL_BASE
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#endif
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#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
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#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
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#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
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#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
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#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
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#define CFG_FLASH_CHECKSUM
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#if defined (CFG_AMD_BOOT)
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#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
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#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
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#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
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#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
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#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
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#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
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#else
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#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
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#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
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#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
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#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
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#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
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#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
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#endif
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#define CONFIG_ENV_OVERWRITE 1
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#if defined CFG_ENV_IS_IN_FLASH
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#undef CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_EEPROM
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#elif defined CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_FLASH
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#undef CFG_ENV_IS_IN_EEPROM
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#elif defined CFG_ENV_IS_IN_EEPROM
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#undef CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_FLASH
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#endif
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#ifndef CFG_JFFS2_FIRST_SECTOR
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#define CFG_JFFS2_FIRST_SECTOR 0
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#endif
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#ifndef CFG_JFFS2_FIRST_BANK
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#define CFG_JFFS2_FIRST_BANK 0
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#endif
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#ifndef CFG_JFFS2_NUM_BANKS
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#define CFG_JFFS2_NUM_BANKS 1
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#endif
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#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
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#define CFG_SRAM_SIZE 0x8000
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/* Use SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
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#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* SDRAM configuration */
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#define CFG_SDRAM_TOTAL_BANKS 2
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#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
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#define CFG_SDRAM_SPD_SIZE 0x40
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#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
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/* SDRAM drive strength register */
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#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
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(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
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(DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
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(DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
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(DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC8220_FEC 1
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#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
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#define CONFIG_PHY_ADDR 0x18
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#endif /* __CONFIG_H */
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