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https://github.com/brain-hackers/u-boot-brain
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26e054c943
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
26 lines
876 B
Makefile
26 lines
876 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += fpga.o
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obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
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obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
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obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
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obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
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obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
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obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
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obj-$(CONFIG_FPGA_XILINX) += xilinx.o
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obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
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ifdef CONFIG_FPGA_ALTERA
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obj-y += altera.o
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obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
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obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
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obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
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obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
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obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
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obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
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endif
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