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https://github.com/brain-hackers/u-boot-brain
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e76cd5d4cf
There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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phys_size_t fixed_sdram(void)
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{
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
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/*
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* Disable memory controller.
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*/
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
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asm ("sync;isync;msync");
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udelay(1000);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
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asm ("sync; isync; msync");
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udelay(1000);
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if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
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/*
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* OK, size detected -> all done
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*/
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return CONFIG_SYS_SDRAM_SIZE<<20;
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}
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return 0; /* nothing found ! */
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}
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#endif
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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