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https://github.com/brain-hackers/u-boot-brain
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1981539914
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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| .. | ||
| arm_pl180_mmci.c | ||
| arm_pl180_mmci.h | ||
| bfin_sdh.c | ||
| davinci_mmc.c | ||
| dw_mmc.c | ||
| exynos_dw_mmc.c | ||
| fsl_esdhc.c | ||
| ftsdc010_esdhc.c | ||
| gen_atmel_mci.c | ||
| Makefile | ||
| mmc_spi.c | ||
| mmc.c | ||
| mv_sdhci.c | ||
| mxcmmc.c | ||
| mxsmmc.c | ||
| omap_hsmmc.c | ||
| pxa_mmc_gen.c | ||
| pxa_mmc.h | ||
| s5p_sdhci.c | ||
| sdhci.c | ||
| sh_mmcif.c | ||
| sh_mmcif.h | ||
| spl_mmc.c | ||
| tegra_mmc.c | ||