mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 02:48:51 +09:00
178 lines
4.6 KiB
C
178 lines
4.6 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#define CFG_NAND_READ_DELAY \
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{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
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extern void board_nand_init(struct nand_chip *nand);
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extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd);
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extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte);
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extern u_char ndfc_read_byte(struct mtd_info *mtdinfo);
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extern int ndfc_dev_ready(struct mtd_info *mtdinfo);
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extern int jump_to_ram(ulong delta);
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extern int jump_to_uboot(ulong addr);
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static int nand_is_bad_block(struct mtd_info *mtd, int block)
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{
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struct nand_chip *this = mtd->priv;
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int page_addr = block * CFG_NAND_PAGE_COUNT;
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, NAND_CMD_READOOB);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Column address */
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this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */
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this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
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this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
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#ifdef CFG_NAND_4_ADDR_CYCLE
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/* One more address cycle for devices > 32MiB */
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this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
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#endif
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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/*
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* Wait a while for the data to be ready
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*/
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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/*
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* Read on byte
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*/
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if (this->read_byte(mtd) != 0xff)
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return 1;
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return 0;
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}
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static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
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{
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struct nand_chip *this = mtd->priv;
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int page_addr = page + block * CFG_NAND_PAGE_COUNT;
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int i;
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, NAND_CMD_READ0);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Column address */
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this->write_byte(mtd, 0); /* A[7:0] */
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this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
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this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
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#ifdef CFG_NAND_4_ADDR_CYCLE
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/* One more address cycle for devices > 32MiB */
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this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
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#endif
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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/*
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* Wait a while for the data to be ready
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*/
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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/*
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* Read page into buffer
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*/
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for (i=0; i<CFG_NAND_PAGE_SIZE; i++)
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*dst++ = this->read_byte(mtd);
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return 0;
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}
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static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
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{
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int block;
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int blockcopy_count;
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int page;
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/*
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* offs has to be aligned to a block address!
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*/
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block = offs / CFG_NAND_BLOCK_SIZE;
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blockcopy_count = 0;
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while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
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if (!nand_is_bad_block(mtd, block)) {
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/*
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* Skip bad blocks
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*/
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for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
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nand_read_page(mtd, block, page, dst);
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dst += CFG_NAND_PAGE_SIZE;
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}
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blockcopy_count++;
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}
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block++;
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}
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return 0;
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}
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void nand_boot(void)
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{
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ulong mem_size;
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struct nand_chip nand_chip;
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nand_info_t nand_info;
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int ret;
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void (*uboot)(void);
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/*
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* Init sdram, so we have access to memory
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*/
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mem_size = initdram(0);
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/*
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* Init board specific nand support
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*/
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nand_info.priv = &nand_chip;
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nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE;
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nand_chip.dev_ready = NULL; /* preset to NULL */
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board_nand_init(&nand_chip);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
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(uchar *)CFG_NAND_U_BOOT_DST);
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/*
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* Jump to U-Boot image
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*/
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uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
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(*uboot)();
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}
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