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![Shaohui Xie](/assets/img/avatar_default.png)
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
202 lines
5.7 KiB
C
202 lines
5.7 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
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* are provided by the three on-board PHY or by the standard Freescale
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* four-port SGMII riser card. We need to change the phy-handle in the
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* kernel dts file to point to the correct PHY according to serdes mux
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* and serdes protocol selection.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fsl_dtsec.h>
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#include "cpld.h"
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#include "../common/fman.h"
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#ifdef CONFIG_FMAN_ENET
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/*
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* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
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* that the mapping must be determined dynamically, or that the lane maps to
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* something other than a board slot
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*/
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static u8 lane_to_slot[] = {
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0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
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};
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static int riser_phy_addr[] = {
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
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};
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/*
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* Initialize the lane_to_slot[] array.
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*
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* On the P2040RDB board the mapping is controlled by CPLD register.
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*/
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static void initialize_lane_to_slot(void)
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{
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u8 mux = CPLD_READ(serdes_mux);
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lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
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lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
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lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
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lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
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}
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/*
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* Given the following ...
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*
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* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
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* compatible string and 'addr' physical address)
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*
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* 2) An Fman port
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*
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* ... update the phy-handle property of the Ethernet node to point to the
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* right PHY. This assumes that we already know the PHY for each port.
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*
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* The offset of the Fman Ethernet node is also passed in for convenience, but
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* it is not used, and we recalculate the offset anyway.
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*
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* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
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* Inside the Fman, "ports" are things that connect to MACs. We only call them
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* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
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* and ports are the same thing.
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*
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*/
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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phy_interface_t intf = fm_info_get_enet_if(port);
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char phy[16];
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/* The RGMII PHY is identified by the MAC connected to it */
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if (intf == PHY_INTERFACE_MODE_RGMII) {
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sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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/* The SGMII PHY is identified by the MAC connected to it */
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if (intf == PHY_INTERFACE_MODE_SGMII) {
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int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
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u8 slot;
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if (lane < 0)
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return;
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slot = lane_to_slot[lane];
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if (slot) {
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sprintf(phy, "phy_sgmii_%x",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
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+ (port - FM1_DTSEC1));
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fdt_set_phy_handle(fdt, compat, addr, phy);
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} else {
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sprintf(phy, "phy_sgmii_%x",
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CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
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+ (port - FM1_DTSEC1));
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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}
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if (intf == PHY_INTERFACE_MODE_XGMII) {
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/* XAUI */
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int lane = serdes_get_first_lane(XAUI_FM1);
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if (lane >= 0) {
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/* The XAUI PHY is identified by the slot */
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sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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}
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}
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#endif /* #ifdef CONFIG_FMAN_ENET */
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct fsl_pq_mdio_info dtsec_mdio_info;
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struct tgec_mdio_info tgec_mdio_info;
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unsigned int i, slot;
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int lane;
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printf("Initializing Fman\n");
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initialize_lane_to_slot();
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the real 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the real 10G MDIO bus */
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fm_tgec_mdio_init(bis, &tgec_mdio_info);
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/*
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* Program the three on-board SGMII PHY addresses. If the SGMII Riser
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* card used, we'll override the PHY address later. For any DTSEC that
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* is RGMII, we'll also override its PHY address later. We assume that
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* DTSEC4 and DTSEC5 are used for RGMII.
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*/
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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if (slot)
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fm_info_set_phy_address(i, riser_phy_addr[i]);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
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fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
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CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
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CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
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break;
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default:
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printf("Fman1: DTSEC%u set to unknown interface %i\n",
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idx + 1, fm_info_get_enet_if(i));
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break;
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}
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fm_info_set_mdio(i,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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}
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lane = serdes_get_first_lane(XAUI_FM1);
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if (lane >= 0) {
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slot = lane_to_slot[lane];
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if (slot)
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fm_info_set_phy_address(FM1_10GEC1,
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CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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}
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fm_info_set_mdio(FM1_10GEC1,
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miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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