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https://github.com/brain-hackers/u-boot-brain
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19014203c4
This adds the DT content that's needed to allow board DTs to enable use of BPMP, clocks, resets, GPIOs, eMMC, and SD cards. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
117 lines
3.1 KiB
Plaintext
117 lines
3.1 KiB
Plaintext
#include "skeleton.dtsi"
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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/ {
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compatible = "nvidia,tegra186";
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#address-cells = <2>;
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#size-cells = <2>;
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gpio_main: gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg =
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<0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts =
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x10000>;
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reg-shift = <2>;
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status = "disabled";
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};
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sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x200>;
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdmmc";
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clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
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clock-names = "sdmmc";
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interrupts = <GIC_SPI 62 0x04>;
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status = "disabled";
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};
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sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x200>;
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resets = <&bpmp TEGRA186_RESET_SDMMC4>;
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reset-names = "sdmmc";
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clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
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clock-names = "sdmmc";
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interrupts = <GIC_SPI 31 0x04>;
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status = "disabled";
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};
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hsp: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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gpio_aon: gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg =
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<0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts =
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sysram@30000000 {
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compatible = "nvidia,tegra186-sysram", "mmio-sram";
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reg = <0x0 0x30000000 0x0 0x50000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
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sysram_cpu_bpmp_tx: shmem@4e000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4e000 0x0 0x1000>;
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};
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sysram_cpu_bpmp_rx: shmem@4f000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4f000 0x0 0x1000>;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
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/*
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* In theory, these references, and the configuration in the
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* node these reference point at, are board-specific, since
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* they depend on the BCT's memory carve-out setup, the
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* firmware that's actually loaded onto the BPMP, etc. However,
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* in practice, all boards are likely to use identical values.
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*/
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shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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};
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