mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
7958a85bca
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
269 lines
6.7 KiB
C
269 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <spl_gpio.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3399.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/periph.h>
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#include <asm/arch-rockchip/sys_proto.h>
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#include <power/regulator.h>
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void board_return_to_bootrom(void)
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{
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
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};
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const char *board_spl_was_booted_from(void)
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{
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u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
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const char *bootdevice_ofpath = NULL;
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if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
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bootdevice_ofpath = boot_devices[bootdevice_brom_id];
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if (bootdevice_ofpath)
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debug("%s: brom_bootdevice_id %x maps to '%s'\n",
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__func__, bootdevice_brom_id, bootdevice_ofpath);
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else
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debug("%s: failed to resolve brom_bootdevice_id %x\n",
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__func__, bootdevice_brom_id);
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return bootdevice_ofpath;
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}
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u32 spl_boot_device(void)
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{
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u32 boot_device = BOOT_DEVICE_MMC1;
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if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
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return BOOT_DEVICE_BOOTROM;
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return boot_device;
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}
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const char *spl_decode_boot_device(u32 boot_device)
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{
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int i;
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static const struct {
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u32 boot_device;
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const char *ofpath;
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} spl_boot_devices_tbl[] = {
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{ BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
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{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
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{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
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};
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for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
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if (spl_boot_devices_tbl[i].boot_device == boot_device)
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return spl_boot_devices_tbl[i].ofpath;
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return NULL;
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}
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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void *blob = spl_image->fdt_addr;
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const char *boot_ofpath;
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int chosen;
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/*
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* Inject the ofpath of the device the full U-Boot (or Linux in
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* Falcon-mode) was booted from into the FDT, if a FDT has been
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* loaded at the same time.
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*/
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if (!blob)
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return;
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boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
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if (!boot_ofpath) {
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pr_err("%s: could not map boot_device to ofpath\n", __func__);
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return;
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}
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chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
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if (chosen < 0) {
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pr_err("%s: could not find/create '/chosen'\n", __func__);
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return;
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}
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fdt_setprop_string(blob, chosen,
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"u-boot,spl-boot-device", boot_ofpath);
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}
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#define TIMER_CHN10_BASE 0xff8680a0
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#define TIMER_END_COUNT_L 0x00
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#define TIMER_END_COUNT_H 0x04
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#define TIMER_INIT_COUNT_L 0x10
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#define TIMER_INIT_COUNT_H 0x14
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0 << 1)
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#define TIMER_RMODE (1 << 1)
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void secure_timer_init(void)
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{
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
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writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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struct rk3399_pmusgrf_regs *sgrf;
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struct rk3399_grf_regs *grf;
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int ret;
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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int sum, i;
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/*
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* Add a delay and ensure that the compiler does not optimise this out.
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* This is needed since the power rails tail a while to turn on, and
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* we get garbage serial output otherwise.
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*/
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sum = 0;
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for (i = 0; i < 150000; i++)
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sum += i;
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gru_dummy_function(sum);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug("U-Boot SPL board init\n");
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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/*
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* Disable DDR and SRAM security regions.
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*
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* As we are entered from the BootROM, the region from
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* 0x0 through 0xfffff (i.e. the first MB of memory) will
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* be protected. This will cause issues with the DW_MMC
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* driver, which tries to DMA from/to the stack (likely)
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* located in this range.
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*/
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sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
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rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
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rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
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/* eMMC clock generator: disable the clock multipilier */
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrreg(&grf->emmccore_con[11], 0x0ff);
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secure_timer_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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pr_err("DRAM init failed: %d\n", ret);
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return;
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}
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}
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#if defined(SPL_GPIO_SUPPORT)
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static void rk3399_force_power_on_reset(void)
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{
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ofnode node;
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struct gpio_desc sysreset_gpio;
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debug("%s: trying to force a power-on reset\n", __func__);
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return;
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}
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if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
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&sysreset_gpio, GPIOD_IS_OUT)) {
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debug("%s: could not find a /config/sysreset-gpio\n", __func__);
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return;
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}
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dm_gpio_set_value(&sysreset_gpio, 1);
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}
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#endif
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void spl_board_init(void)
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{
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#if defined(SPL_GPIO_SUPPORT)
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struct rk3399_cru *cru = rockchip_get_cru();
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/*
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* The RK3399 resets only 'almost all logic' (see also in the TRM
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* "3.9.4 Global software reset"), when issuing a software reset.
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* This may cause issues during boot-up for some configurations of
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* the application software stack.
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*
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* To work around this, we test whether the last reset reason was
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* a power-on reset and (if not) issue an overtemp-reset to reset
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* the entire module.
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*
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* While this was previously fixed by modifying the various places
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* that could generate a software reset (e.g. U-Boot's sysreset
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* driver, the ATF or Linux), we now have it here to ensure that
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* we no longer have to track this through the various components.
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*/
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if (cru->glb_rst_st != 0)
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rk3399_force_power_on_reset();
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#endif
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#if defined(SPL_DM_REGULATOR)
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/*
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* Turning the eMMC and SPI back on (if disabled via the Qseven
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* BIOS_ENABLE) signal is done through a always-on regulator).
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*/
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if (regulators_enable_boot_on(false))
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debug("%s: Cannot enable boot on regulator\n", __func__);
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#endif
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preloader_console_init();
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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