mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
acea123825
We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
77 lines
1.6 KiB
C
77 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/hardware.h>
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_MMC1;
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}
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u32 spl_boot_mode(const u32 boot_device)
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{
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return MMCSD_MODE_RAW;
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}
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#define TIMER_LOAD_COUNT_L 0x00
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#define TIMER_LOAD_COUNT_H 0x04
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(COUNTER_FREQUENCY));
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
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TIMER_CONTROL_REG);
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}
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#define SGRF_DDR_CON0 0x10150000
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret) {
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printf("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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/* Init secure timer */
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rockchip_stimer_init();
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/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
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timer_init();
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/* Disable the ddr secure region setting to make it non-secure */
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rk_clrreg(SGRF_DDR_CON0, 0x4000);
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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