Ilya Yanok 189a6956eb ehci-hcd: fix external buffer cache handling ... Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done: 1. Remove useless length alignment check. We get actual transfer length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>		2012-07-18 14:43:42 +02:00
..
eth	drivers/usb/eth/asix.c: Fix build warning	2012-05-22 10:18:14 -05:00
gadget	net: Fix remaining API interface breakage	2012-05-23 14:19:21 -05:00
host	ehci-hcd: fix external buffer cache handling	2012-07-18 14:43:42 +02:00
musb	ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment	2012-07-18 14:43:29 +02:00
phy	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
ulpi	usb: ulpi: Add omap-ulpi-view port support	2012-02-12 10:11:30 +01:00