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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
![Claudiu Manoil](/assets/img/avatar_default.png)
Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
689 lines
18 KiB
C
689 lines
18 KiB
C
/*
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* Freescale Three Speed Ethernet Controller driver
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* author Andy Fleming
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#include <tsec.h>
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#include <fsl_mdio.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define TX_BUF_CNT 2
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static uint rx_idx; /* index of the current RX buffer */
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static uint tx_idx; /* index of the current TX buffer */
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#ifdef __GNUC__
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static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
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static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
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#else
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#error "rtx must be 64-bit aligned"
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#endif
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static int tsec_send(struct eth_device *dev, void *packet, int length);
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/* Default initializations for TSEC controllers. */
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static struct tsec_info_struct tsec_info[] = {
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#ifdef CONFIG_TSEC1
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STD_TSEC_INFO(1), /* TSEC1 */
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#endif
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#ifdef CONFIG_TSEC2
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STD_TSEC_INFO(2), /* TSEC2 */
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#endif
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#ifdef CONFIG_MPC85XX_FEC
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{
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.regs = TSEC_GET_REGS(2, 0x2000),
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.devname = CONFIG_MPC85XX_FEC_NAME,
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.phyaddr = FEC_PHY_ADDR,
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.flags = FEC_FLAGS,
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.mii_devname = DEFAULT_MII_NAME
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}, /* FEC */
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#endif
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#ifdef CONFIG_TSEC3
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STD_TSEC_INFO(3), /* TSEC3 */
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#endif
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#ifdef CONFIG_TSEC4
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STD_TSEC_INFO(4), /* TSEC4 */
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#endif
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};
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#define TBIANA_SETTINGS ( \
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TBIANA_ASYMMETRIC_PAUSE \
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| TBIANA_SYMMETRIC_PAUSE \
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| TBIANA_FULL_DUPLEX \
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)
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/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
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#ifndef CONFIG_TSEC_TBICR_SETTINGS
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#define CONFIG_TSEC_TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_ANEG_ENABLE \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
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#endif /* CONFIG_TSEC_TBICR_SETTINGS */
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/* Configure the TBI for SGMII operation */
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static void tsec_configure_serdes(struct tsec_private *priv)
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{
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/* Access TBI PHY registers at given TSEC register offset as opposed
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* to the register offset used for external PHY accesses */
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_ANA, TBIANA_SETTINGS);
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_TBICON, TBICON_CLK_SELECT);
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
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}
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#ifdef CONFIG_MCAST_TFTP
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/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
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/* Set the appropriate hash bit for the given addr */
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/* The algorithm works like so:
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* 1) Take the Destination Address (ie the multicast address), and
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* do a CRC on it (little endian), and reverse the bits of the
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* result.
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* 2) Use the 8 most significant bits as a hash into a 256-entry
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* table. The table is controlled through 8 32-bit registers:
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* gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
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* 255. This means that the 3 most significant bits in the
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* hash index which gaddr register to use, and the 5 other bits
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* indicate which bit (assuming an IBM numbering scheme, which
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* for PowerPC (tm) is usually the case) in the register holds
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* the entry. */
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static int
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tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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u32 result, value;
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u8 whichbit, whichreg;
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result = ether_crc(MAC_ADDR_LEN, mcast_mac);
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whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
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whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
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value = 1 << (31-whichbit);
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if (set)
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setbits_be32(®s->hash.gaddr0 + whichreg, value);
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else
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clrbits_be32(®s->hash.gaddr0 + whichreg, value);
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return 0;
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}
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#endif /* Multicast TFTP ? */
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/* Initialized required registers to appropriate values, zeroing
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* those we don't care about (unless zero is bad, in which case,
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* choose a more appropriate value)
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*/
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static void init_registers(struct tsec __iomem *regs)
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{
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/* Clear IEVENT */
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out_be32(®s->ievent, IEVENT_INIT_CLEAR);
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out_be32(®s->imask, IMASK_INIT_CLEAR);
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out_be32(®s->hash.iaddr0, 0);
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out_be32(®s->hash.iaddr1, 0);
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out_be32(®s->hash.iaddr2, 0);
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out_be32(®s->hash.iaddr3, 0);
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out_be32(®s->hash.iaddr4, 0);
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out_be32(®s->hash.iaddr5, 0);
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out_be32(®s->hash.iaddr6, 0);
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out_be32(®s->hash.iaddr7, 0);
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out_be32(®s->hash.gaddr0, 0);
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out_be32(®s->hash.gaddr1, 0);
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out_be32(®s->hash.gaddr2, 0);
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out_be32(®s->hash.gaddr3, 0);
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out_be32(®s->hash.gaddr4, 0);
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out_be32(®s->hash.gaddr5, 0);
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out_be32(®s->hash.gaddr6, 0);
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out_be32(®s->hash.gaddr7, 0);
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out_be32(®s->rctrl, 0x00000000);
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/* Init RMON mib registers */
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memset((void *)®s->rmon, 0, sizeof(regs->rmon));
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out_be32(®s->rmon.cam1, 0xffffffff);
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out_be32(®s->rmon.cam2, 0xffffffff);
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out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
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out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
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out_be32(®s->attr, ATTR_INIT_SETTINGS);
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out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
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}
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/* Configure maccfg2 based on negotiated speed and duplex
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* reported by PHY handling code
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*/
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static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
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{
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struct tsec __iomem *regs = priv->regs;
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u32 ecntrl, maccfg2;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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/* clear all bits relative with interface mode */
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ecntrl = in_be32(®s->ecntrl);
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ecntrl &= ~ECNTRL_R100;
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maccfg2 = in_be32(®s->maccfg2);
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maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
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if (phydev->duplex)
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maccfg2 |= MACCFG2_FULL_DUPLEX;
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switch (phydev->speed) {
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case 1000:
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maccfg2 |= MACCFG2_GMII;
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break;
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case 100:
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case 10:
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maccfg2 |= MACCFG2_MII;
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/* Set R100 bit in all modes although
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* it is only used in RGMII mode
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*/
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if (phydev->speed == 100)
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ecntrl |= ECNTRL_R100;
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break;
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default:
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printf("%s: Speed was bad\n", phydev->dev->name);
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break;
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}
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out_be32(®s->ecntrl, ecntrl);
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out_be32(®s->maccfg2, maccfg2);
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printf("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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/*
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* When MACCFG1[Rx_EN] is enabled during system boot as part
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* of the eTSEC port initialization sequence,
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* the eTSEC Rx logic may not be properly initialized.
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*/
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void redundant_init(struct eth_device *dev)
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{
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struct tsec_private *priv = dev->priv;
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struct tsec __iomem *regs = priv->regs;
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uint t, count = 0;
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int fail = 1;
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static const u8 pkt[] = {
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0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
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0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
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0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
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0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
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0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
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0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
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0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
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0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
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0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
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0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
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0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
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0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
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0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
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0x71, 0x72};
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/* Enable promiscuous mode */
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setbits_be32(®s->rctrl, 0x8);
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/* Enable loopback mode */
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setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
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/* Enable transmit and receive */
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setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
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/* Tell the DMA it is clear to go */
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setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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do {
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uint16_t status;
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tsec_send(dev, (void *)pkt, sizeof(pkt));
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/* Wait for buffer to be received */
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for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
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if (t >= 10 * TOUT_LOOP) {
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printf("%s: tsec: rx error\n", dev->name);
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break;
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}
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}
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if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt)))
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fail = 0;
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out_be16(&rxbd[rx_idx].length, 0);
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status = RXBD_EMPTY;
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if ((rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&rxbd[rx_idx].status, status);
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rx_idx = (rx_idx + 1) % PKTBUFSRX;
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if (in_be32(®s->ievent) & IEVENT_BSY) {
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out_be32(®s->ievent, IEVENT_BSY);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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}
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if (fail) {
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printf("loopback recv packet error!\n");
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clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
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udelay(1000);
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setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
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}
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} while ((count++ < 4) && (fail == 1));
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if (fail)
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panic("eTSEC init fail!\n");
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/* Disable promiscuous mode */
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clrbits_be32(®s->rctrl, 0x8);
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/* Disable loopback mode */
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clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
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}
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#endif
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/* Set up the buffers and their descriptors, and bring up the
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* interface
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*/
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static void startup_tsec(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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uint16_t status;
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int i;
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/* reset the indices to zero */
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rx_idx = 0;
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tx_idx = 0;
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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uint svr;
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#endif
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/* Point to the buffer descriptors */
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out_be32(®s->tbase, (u32)&txbd[0]);
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out_be32(®s->rbase, (u32)&rxbd[0]);
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/* Initialize the Rx Buffer descriptors */
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for (i = 0; i < PKTBUFSRX; i++) {
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out_be16(&rxbd[i].status, RXBD_EMPTY);
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out_be16(&rxbd[i].length, 0);
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out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]);
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}
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status = in_be16(&rxbd[PKTBUFSRX - 1].status);
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out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
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/* Initialize the TX Buffer Descriptors */
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for (i = 0; i < TX_BUF_CNT; i++) {
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out_be16(&txbd[i].status, 0);
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out_be16(&txbd[i].length, 0);
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out_be32(&txbd[i].bufptr, 0);
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}
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status = in_be16(&txbd[TX_BUF_CNT - 1].status);
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out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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svr = get_svr();
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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redundant_init(dev);
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#endif
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/* Enable Transmit and Receive */
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setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
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/* Tell the DMA it is clear to go */
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setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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}
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/* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* errors
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*/
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static int tsec_send(struct eth_device *dev, void *packet, int length)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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uint16_t status;
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int result = 0;
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int i;
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/* Find an empty buffer descriptor */
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for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx buffers full\n", dev->name);
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return result;
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}
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}
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out_be32(&txbd[tx_idx].bufptr, (u32)packet);
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out_be16(&txbd[tx_idx].length, length);
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status = in_be16(&txbd[tx_idx].status);
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out_be16(&txbd[tx_idx].status, status |
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
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/* Tell the DMA to go */
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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/* Wait for buffer to be transmitted */
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for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx error\n", dev->name);
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return result;
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}
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}
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tx_idx = (tx_idx + 1) % TX_BUF_CNT;
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result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
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return result;
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}
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static int tsec_recv(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
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int length = in_be16(&rxbd[rx_idx].length);
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uint16_t status = in_be16(&rxbd[rx_idx].status);
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/* Send the packet up if there were no errors */
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if (!(status & RXBD_STATS))
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NetReceive(NetRxPackets[rx_idx], length - 4);
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else
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printf("Got error %x\n", (status & RXBD_STATS));
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out_be16(&rxbd[rx_idx].length, 0);
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status = RXBD_EMPTY;
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/* Set the wrap bit if this is the last element in the list */
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if ((rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&rxbd[rx_idx].status, status);
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rx_idx = (rx_idx + 1) % PKTBUFSRX;
|
|
}
|
|
|
|
if (in_be32(®s->ievent) & IEVENT_BSY) {
|
|
out_be32(®s->ievent, IEVENT_BSY);
|
|
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
/* Stop the interface */
|
|
static void tsec_halt(struct eth_device *dev)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
struct tsec __iomem *regs = priv->regs;
|
|
|
|
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
|
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
|
|
|
while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
|
|
!= (IEVENT_GRSC | IEVENT_GTSC))
|
|
;
|
|
|
|
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
|
|
|
|
/* Shut down the PHY, as needed */
|
|
phy_shutdown(priv->phydev);
|
|
}
|
|
|
|
/* Initializes data structures and registers for the controller,
|
|
* and brings the interface up. Returns the link status, meaning
|
|
* that it returns success if the link is up, failure otherwise.
|
|
* This allows u-boot to find the first active controller.
|
|
*/
|
|
static int tsec_init(struct eth_device *dev, bd_t * bd)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u32 tempval;
|
|
int ret;
|
|
|
|
/* Make sure the controller is stopped */
|
|
tsec_halt(dev);
|
|
|
|
/* Init MACCFG2. Defaults to GMII */
|
|
out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
|
|
|
|
/* Init ECNTRL */
|
|
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
|
|
|
|
/* Copy the station address into the address registers.
|
|
* For a station address of 0x12345678ABCD in transmission
|
|
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
|
|
* MACnADDR2 is set to 0x34120000.
|
|
*/
|
|
tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
|
|
(dev->enetaddr[3] << 8) | dev->enetaddr[2];
|
|
|
|
out_be32(®s->macstnaddr1, tempval);
|
|
|
|
tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
|
|
|
|
out_be32(®s->macstnaddr2, tempval);
|
|
|
|
/* Clear out (for the most part) the other registers */
|
|
init_registers(regs);
|
|
|
|
/* Ready the device for tx/rx */
|
|
startup_tsec(dev);
|
|
|
|
/* Start up the PHY */
|
|
ret = phy_startup(priv->phydev);
|
|
if (ret) {
|
|
printf("Could not initialize PHY %s\n",
|
|
priv->phydev->dev->name);
|
|
return ret;
|
|
}
|
|
|
|
adjust_link(priv, priv->phydev);
|
|
|
|
/* If there's no link, fail */
|
|
return priv->phydev->link ? 0 : -1;
|
|
}
|
|
|
|
static phy_interface_t tsec_get_interface(struct tsec_private *priv)
|
|
{
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u32 ecntrl;
|
|
|
|
ecntrl = in_be32(®s->ecntrl);
|
|
|
|
if (ecntrl & ECNTRL_SGMII_MODE)
|
|
return PHY_INTERFACE_MODE_SGMII;
|
|
|
|
if (ecntrl & ECNTRL_TBI_MODE) {
|
|
if (ecntrl & ECNTRL_REDUCED_MODE)
|
|
return PHY_INTERFACE_MODE_RTBI;
|
|
else
|
|
return PHY_INTERFACE_MODE_TBI;
|
|
}
|
|
|
|
if (ecntrl & ECNTRL_REDUCED_MODE) {
|
|
if (ecntrl & ECNTRL_REDUCED_MII_MODE)
|
|
return PHY_INTERFACE_MODE_RMII;
|
|
else {
|
|
phy_interface_t interface = priv->interface;
|
|
|
|
/*
|
|
* This isn't autodetected, so it must
|
|
* be set by the platform code.
|
|
*/
|
|
if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
|
|
(interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
|
|
(interface == PHY_INTERFACE_MODE_RGMII_RXID))
|
|
return interface;
|
|
|
|
return PHY_INTERFACE_MODE_RGMII;
|
|
}
|
|
}
|
|
|
|
if (priv->flags & TSEC_GIGABIT)
|
|
return PHY_INTERFACE_MODE_GMII;
|
|
|
|
return PHY_INTERFACE_MODE_MII;
|
|
}
|
|
|
|
|
|
/* Discover which PHY is attached to the device, and configure it
|
|
* properly. If the PHY is not recognized, then return 0
|
|
* (failure). Otherwise, return 1
|
|
*/
|
|
static int init_phy(struct eth_device *dev)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
struct phy_device *phydev;
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u32 supported = (SUPPORTED_10baseT_Half |
|
|
SUPPORTED_10baseT_Full |
|
|
SUPPORTED_100baseT_Half |
|
|
SUPPORTED_100baseT_Full);
|
|
|
|
if (priv->flags & TSEC_GIGABIT)
|
|
supported |= SUPPORTED_1000baseT_Full;
|
|
|
|
/* Assign a Physical address to the TBI */
|
|
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
|
|
|
|
priv->interface = tsec_get_interface(priv);
|
|
|
|
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
|
|
tsec_configure_serdes(priv);
|
|
|
|
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
|
|
|
|
phydev->supported &= supported;
|
|
phydev->advertising = phydev->supported;
|
|
|
|
priv->phydev = phydev;
|
|
|
|
phy_config(phydev);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* Initialize device structure. Returns success if PHY
|
|
* initialization succeeded (i.e. if it recognizes the PHY)
|
|
*/
|
|
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
|
|
{
|
|
struct eth_device *dev;
|
|
int i;
|
|
struct tsec_private *priv;
|
|
|
|
dev = (struct eth_device *)malloc(sizeof *dev);
|
|
|
|
if (NULL == dev)
|
|
return 0;
|
|
|
|
memset(dev, 0, sizeof *dev);
|
|
|
|
priv = (struct tsec_private *)malloc(sizeof(*priv));
|
|
|
|
if (NULL == priv)
|
|
return 0;
|
|
|
|
priv->regs = tsec_info->regs;
|
|
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
|
|
|
|
priv->phyaddr = tsec_info->phyaddr;
|
|
priv->flags = tsec_info->flags;
|
|
|
|
sprintf(dev->name, tsec_info->devname);
|
|
priv->interface = tsec_info->interface;
|
|
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
|
|
dev->iobase = 0;
|
|
dev->priv = priv;
|
|
dev->init = tsec_init;
|
|
dev->halt = tsec_halt;
|
|
dev->send = tsec_send;
|
|
dev->recv = tsec_recv;
|
|
#ifdef CONFIG_MCAST_TFTP
|
|
dev->mcast = tsec_mcast_addr;
|
|
#endif
|
|
|
|
/* Tell u-boot to get the addr from the env */
|
|
for (i = 0; i < 6; i++)
|
|
dev->enetaddr[i] = 0;
|
|
|
|
eth_register(dev);
|
|
|
|
/* Reset the MAC */
|
|
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
|
|
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
|
|
/* Try to initialize PHY here, and return */
|
|
return init_phy(dev);
|
|
}
|
|
|
|
/*
|
|
* Initialize all the TSEC devices
|
|
*
|
|
* Returns the number of TSEC devices that were initialized
|
|
*/
|
|
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
|
|
{
|
|
int i;
|
|
int ret, count = 0;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
ret = tsec_initialize(bis, &tsecs[i]);
|
|
if (ret > 0)
|
|
count += ret;
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
int tsec_standard_init(bd_t *bis)
|
|
{
|
|
struct fsl_pq_mdio_info info;
|
|
|
|
info.regs = TSEC_GET_MDIO_REGS_BASE(1);
|
|
info.name = DEFAULT_MII_NAME;
|
|
|
|
fsl_pq_mdio_init(bis, &info);
|
|
|
|
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
|
|
}
|