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![Allen Martin](/assets/img/avatar_default.png)
Add support for configuring tegra SPI driver from devicetree. Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts file for spi controller to describe seaboard spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
331 lines
8.3 KiB
C
331 lines
8.3 KiB
C
/*
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* Copyright (c) 2010-2012 NVIDIA Corporation
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* With help from the mpc8xxx SPI driver
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* With more help from omap3_spi SPI driver
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/uart-spi-switch.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/tegra_spi.h>
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#include <spi.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPI_CORRUPTS_UART)
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#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
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#else
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#define corrupt_delay()
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#endif
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struct tegra_spi_slave {
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struct spi_slave slave;
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struct spi_tegra *regs;
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unsigned int freq;
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unsigned int mode;
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int periph_id;
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};
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static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct tegra_spi_slave, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
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if (bus != 0 || cs != 0)
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return 0;
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else
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return 1;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct tegra_spi_slave *spi;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("SPI error: unsupported bus %d / chip select %d\n",
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bus, cs);
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return NULL;
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}
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if (max_hz > TEGRA_SPI_MAX_FREQ) {
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printf("SPI error: unsupported frequency %d Hz. Max frequency"
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" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
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return NULL;
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}
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spi = malloc(sizeof(struct tegra_spi_slave));
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if (!spi) {
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printf("SPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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spi->slave.bus = bus;
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spi->slave.cs = cs;
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#ifdef CONFIG_OF_CONTROL
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int node = fdtdec_next_compatible(gd->fdt_blob, 0,
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COMPAT_NVIDIA_TEGRA20_SFLASH);
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if (node < 0) {
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debug("%s: cannot locate sflash node\n", __func__);
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return NULL;
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}
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if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
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debug("%s: sflash is disabled\n", __func__);
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return NULL;
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}
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spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
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node, "reg");
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if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
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debug("%s: no sflash register found\n", __func__);
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return NULL;
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}
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spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
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if (!spi->freq) {
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debug("%s: no sflash max frequency found\n", __func__);
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return NULL;
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}
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spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
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if (spi->periph_id == PERIPH_ID_NONE) {
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debug("%s: could not decode periph id\n", __func__);
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return NULL;
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}
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#else
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spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
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spi->freq = TEGRA_SPI_MAX_FREQ;
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spi->periph_id = PERIPH_ID_SPI1;
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#endif
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if (max_hz < spi->freq) {
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debug("%s: limiting frequency from %u to %u\n", __func__,
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spi->freq, max_hz);
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spi->freq = max_hz;
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}
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debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
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__func__, spi->regs, spi->freq, spi->periph_id);
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spi->mode = mode;
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return &spi->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct tegra_spi_slave *spi = to_tegra_spi(slave);
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free(spi);
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}
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void spi_init(void)
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{
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/* do nothing */
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct tegra_spi_slave *spi = to_tegra_spi(slave);
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struct spi_tegra *regs = spi->regs;
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u32 reg;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
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/* Clear stale status here */
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reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
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SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
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writel(reg, ®s->status);
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debug("spi_init: STATUS = %08x\n", readl(®s->status));
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/*
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* Use sw-controlled CS, so we can clock in data after ReadID, etc.
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*/
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reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
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if (spi->mode & 2)
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reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
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clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
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SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
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debug("spi_init: COMMAND = %08x\n", readl(®s->command));
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/*
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* SPI pins on Tegra20 are muxed - change pinmux later due to UART
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* issue.
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*/
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pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
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pinmux_tristate_disable(PINGRP_LSPI);
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#ifndef CONFIG_SPI_UART_SWITCH
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/*
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* NOTE:
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* Only set PinMux bits 3:2 to SPI here on boards that don't have the
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* SPI UART switch or subsequent UART data won't go out! See
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* spi_uart_switch().
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*/
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/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
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#endif
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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/*
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* We can't release UART_DISABLE and set pinmux to UART4 here since
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* some code (e,g, spi_flash_probe) uses printf() while the SPI
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* bus is held. That is arguably bad, but it has the advantage of
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* already being in the source tree.
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*/
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct tegra_spi_slave *spi = to_tegra_spi(slave);
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pinmux_select_spi();
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/* CS is negated on Tegra, so drive a 1 to get a 0 */
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setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
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corrupt_delay(); /* Let UART settle */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct tegra_spi_slave *spi = to_tegra_spi(slave);
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pinmux_select_uart();
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/* CS is negated on Tegra, so drive a 0 to get a 1 */
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clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
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corrupt_delay(); /* Let SPI settle */
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags)
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{
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struct tegra_spi_slave *spi = to_tegra_spi(slave);
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struct spi_tegra *regs = spi->regs;
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u32 reg, tmpdout, tmpdin = 0;
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const u8 *dout = data_out;
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u8 *din = data_in;
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int num_bytes;
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int ret;
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debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
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slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
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if (bitlen % 8)
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return -1;
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num_bytes = bitlen / 8;
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ret = 0;
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reg = readl(®s->status);
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writel(reg, ®s->status); /* Clear all SPI events via R/W */
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debug("spi_xfer entry: STATUS = %08x\n", reg);
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reg = readl(®s->command);
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reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
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writel(reg, ®s->command);
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debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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/* handle data in 32-bit chunks */
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while (num_bytes > 0) {
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int bytes;
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int is_read = 0;
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int tm, i;
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tmpdout = 0;
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bytes = (num_bytes > 4) ? 4 : num_bytes;
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if (dout != NULL) {
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for (i = 0; i < bytes; ++i)
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tmpdout = (tmpdout << 8) | dout[i];
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}
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num_bytes -= bytes;
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if (dout)
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dout += bytes;
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clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
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bytes * 8 - 1);
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writel(tmpdout, ®s->tx_fifo);
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setbits_le32(®s->command, SPI_CMD_GO);
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/*
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* Wait for SPI transmit FIFO to empty, or to time out.
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* The RX FIFO status will be read and cleared last
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*/
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for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
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u32 status;
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status = readl(®s->status);
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/* We can exit when we've had both RX and TX activity */
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if (is_read && (status & SPI_STAT_TXF_EMPTY))
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break;
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if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
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SPI_STAT_RDY)
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tm++;
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else if (!(status & SPI_STAT_RXF_EMPTY)) {
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tmpdin = readl(®s->rx_fifo);
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is_read = 1;
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/* swap bytes read in */
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if (din != NULL) {
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for (i = bytes - 1; i >= 0; --i) {
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din[i] = tmpdin & 0xff;
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tmpdin >>= 8;
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}
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din += bytes;
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}
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}
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}
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if (tm >= SPI_TIMEOUT)
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ret = tm;
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/* clear ACK RDY, etc. bits */
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writel(readl(®s->status), ®s->status);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
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tmpdin, readl(®s->status));
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if (ret) {
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printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
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return -1;
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}
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return 0;
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}
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