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![Michal Simek](/assets/img/avatar_default.png)
Device driver for Zynq Gem IP. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
441 lines
12 KiB
C
441 lines
12 KiB
C
/*
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* (C) Copyright 2011 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* Based on Xilinx gmac driver:
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* (C) Copyright 2011 Xilinx
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <net.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <watchdog.h>
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#if !defined(CONFIG_PHYLIB)
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# error XILINX_GEM_ETHERNET requires PHYLIB
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#endif
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/* Bit/mask specification */
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#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
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#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
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#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
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#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
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#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
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#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
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#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
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#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
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#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
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#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
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#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
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/* Wrap bit, last descriptor */
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#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
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#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
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#define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */
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#define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */
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/* Transmit buffs exhausted mid frame */
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#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010
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#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
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#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
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#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
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#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
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#define ZYNQ_GEM_NWCFG_SPEED 0x00000001 /* 100 Mbps operation */
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#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
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#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_SPEED | \
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ZYNQ_GEM_NWCFG_FDEN | \
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ZYNQ_GEM_NWCFG_FSREM | \
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ZYNQ_GEM_NWCFG_MDCCLKDIV)
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#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
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#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
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/* Use full configured addressable space (8 Kb) */
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#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
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/* Use full configured addressable space (4 Kb) */
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#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
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/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
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#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
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#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
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ZYNQ_GEM_DMACR_RXSIZE | \
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ZYNQ_GEM_DMACR_TXSIZE | \
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ZYNQ_GEM_DMACR_RXBUF)
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/* Device registers */
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struct zynq_gem_regs {
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u32 nwctrl; /* Network Control reg */
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u32 nwcfg; /* Network Config reg */
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u32 nwsr; /* Network Status reg */
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u32 reserved1;
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u32 dmacr; /* DMA Control reg */
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u32 txsr; /* TX Status reg */
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u32 rxqbase; /* RX Q Base address reg */
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u32 txqbase; /* TX Q Base address reg */
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u32 rxsr; /* RX Status reg */
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u32 reserved2[2];
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u32 idr; /* Interrupt Disable reg */
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u32 reserved3;
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u32 phymntnc; /* Phy Maintaince reg */
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u32 reserved4[18];
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u32 hashl; /* Hash Low address reg */
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u32 hashh; /* Hash High address reg */
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#define LADDR_LOW 0
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#define LADDR_HIGH 1
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u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
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u32 match[4]; /* Type ID1 Match reg */
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u32 reserved6[18];
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u32 stat[44]; /* Octects transmitted Low reg - stat start */
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};
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/* BD descriptors */
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struct emac_bd {
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u32 addr; /* Next descriptor pointer */
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u32 status;
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};
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#define RX_BUF 3
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/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
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struct zynq_gem_priv {
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struct emac_bd tx_bd;
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struct emac_bd rx_bd[RX_BUF];
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char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
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u32 rxbd_current;
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u32 rx_first_buf;
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int phyaddr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static inline int mdio_wait(struct eth_device *dev)
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{
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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u32 timeout = 200;
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/* Wait till MDIO interface is ready to accept a new transaction. */
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while (--timeout) {
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if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
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break;
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WATCHDOG_RESET();
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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return 0;
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}
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static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
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u32 op, u16 *data)
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{
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u32 mgtcr;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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if (mdio_wait(dev))
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return 1;
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/* Construct mgtcr mask for the operation */
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mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
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(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
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(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
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/* Write mgtcr and wait for completion */
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writel(mgtcr, ®s->phymntnc);
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if (mdio_wait(dev))
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return 1;
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if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
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*data = readl(®s->phymntnc);
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return 0;
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}
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static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
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{
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return phy_setup_op(dev, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
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}
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static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
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{
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return phy_setup_op(dev, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
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}
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static int zynq_gem_setup_mac(struct eth_device *dev)
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{
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u32 i, macaddrlow, macaddrhigh;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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/* Set the MAC bits [31:0] in BOT */
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macaddrlow = dev->enetaddr[0];
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macaddrlow |= dev->enetaddr[1] << 8;
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macaddrlow |= dev->enetaddr[2] << 16;
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macaddrlow |= dev->enetaddr[3] << 24;
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/* Set MAC bits [47:32] in TOP */
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macaddrhigh = dev->enetaddr[4];
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macaddrhigh |= dev->enetaddr[5] << 8;
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for (i = 0; i < 4; i++) {
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writel(0, ®s->laddr[i][LADDR_LOW]);
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writel(0, ®s->laddr[i][LADDR_HIGH]);
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/* Do not use MATCHx register */
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writel(0, ®s->match[i]);
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}
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writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
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writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
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return 0;
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}
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static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
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{
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u32 i;
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struct phy_device *phydev;
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const u32 stat_size = (sizeof(struct zynq_gem_regs) -
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offsetof(struct zynq_gem_regs, stat)) / 4;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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struct zynq_gem_priv *priv = dev->priv;
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const u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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/* Disable all interrupts */
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writel(0xFFFFFFFF, ®s->idr);
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/* Disable the receiver & transmitter */
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writel(0, ®s->nwctrl);
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writel(0, ®s->txsr);
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writel(0, ®s->rxsr);
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writel(0, ®s->phymntnc);
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/* Clear the Hash registers for the mac address pointed by AddressPtr */
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writel(0x0, ®s->hashl);
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/* Write bits [63:32] in TOP */
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writel(0x0, ®s->hashh);
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/* Clear all counters */
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for (i = 0; i <= stat_size; i++)
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readl(®s->stat[i]);
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/* Setup RxBD space */
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memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
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/* Create the RxBD ring */
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memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
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for (i = 0; i < RX_BUF; i++) {
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priv->rx_bd[i].status = 0xF0000000;
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priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
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(i * PKTSIZE_ALIGN));
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}
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/* WRAP bit to last BD */
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priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
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/* Write RxBDs to IP */
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writel((u32) &(priv->rx_bd), ®s->rxqbase);
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/* MAC Setup */
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/* Setup Network Configuration register */
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writel(ZYNQ_GEM_NWCFG_INIT, ®s->nwcfg);
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/* Setup for DMA Configuration register */
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writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
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/* Setup for Network Control register, MDIO, Rx and Tx enable */
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK |
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ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK);
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/* interface - look at tsec */
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
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phydev->supported &= supported;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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phy_startup(phydev);
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return 0;
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}
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static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
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{
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u32 status;
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struct zynq_gem_priv *priv = dev->priv;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \
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ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK;
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/* setup BD */
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writel((u32)&(priv->tx_bd), ®s->txqbase);
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/* Setup Tx BD */
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memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd));
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priv->tx_bd.addr = (u32)ptr;
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priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK |
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ZYNQ_GEM_TXBUF_WRAP_MASK;
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/* Start transmit */
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
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/* Read the stat register to know if the packet has been transmitted */
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status = readl(®s->txsr);
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if (status & mask)
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printf("Something has gone wrong here!? Status is 0x%x.\n",
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status);
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/* Clear Tx status register before leaving . */
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writel(status, ®s->txsr);
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return 0;
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}
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/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
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static int zynq_gem_recv(struct eth_device *dev)
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{
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int frame_len;
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struct zynq_gem_priv *priv = dev->priv;
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struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
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struct emac_bd *first_bd;
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if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
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return 0;
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if (!(current_bd->status &
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(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
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printf("GEM: SOF or EOF not set for last buffer received!\n");
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return 0;
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}
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frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
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if (frame_len) {
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NetReceive((u8 *) (current_bd->addr &
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ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
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if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
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priv->rx_first_buf = priv->rxbd_current;
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else {
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current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
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current_bd->status = 0xF0000000; /* FIXME */
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}
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if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
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first_bd = &priv->rx_bd[priv->rx_first_buf];
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first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
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first_bd->status = 0xF0000000;
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}
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if ((++priv->rxbd_current) >= RX_BUF)
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priv->rxbd_current = 0;
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return frame_len;
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}
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return 0;
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}
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static void zynq_gem_halt(struct eth_device *dev)
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{
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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/* Disable the receiver & transmitter */
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writel(0, ®s->nwctrl);
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}
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static int zynq_gem_miiphyread(const char *devname, uchar addr,
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uchar reg, ushort *val)
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{
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struct eth_device *dev = eth_get_dev();
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int ret;
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ret = phyread(dev, addr, reg, val);
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debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
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return ret;
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}
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static int zynq_gem_miiphy_write(const char *devname, uchar addr,
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uchar reg, ushort val)
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{
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struct eth_device *dev = eth_get_dev();
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debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
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return phywrite(dev, addr, reg, val);
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}
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int zynq_gem_initialize(bd_t *bis, int base_addr)
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{
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struct eth_device *dev;
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struct zynq_gem_priv *priv;
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dev = calloc(1, sizeof(*dev));
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if (dev == NULL)
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return -1;
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dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
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if (dev->priv == NULL) {
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free(dev);
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return -1;
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}
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priv = dev->priv;
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#ifdef CONFIG_PHY_ADDR
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priv->phyaddr = CONFIG_PHY_ADDR;
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#else
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priv->phyaddr = -1;
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#endif
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sprintf(dev->name, "Gem.%x", base_addr);
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dev->iobase = base_addr;
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dev->init = zynq_gem_init;
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dev->halt = zynq_gem_halt;
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dev->send = zynq_gem_send;
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dev->recv = zynq_gem_recv;
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dev->write_hwaddr = zynq_gem_setup_mac;
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eth_register(dev);
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miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
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priv->bus = miiphy_get_dev_by_name(dev->name);
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return 1;
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}
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