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https://github.com/brain-hackers/u-boot-brain
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6eb32a03e0
Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
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* Jun-jie Zhang <b18070@freescale.com>
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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#ifndef __FSL_PHY_H__
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#define __FSL_PHY_H__
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#include <net.h>
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#include <miiphy.h>
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struct tsec_mii_mng {
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u32 miimcfg; /* MII management configuration reg */
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u32 miimcom; /* MII management command reg */
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u32 miimadd; /* MII management address reg */
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u32 miimcon; /* MII management control reg */
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u32 miimstat; /* MII management status reg */
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u32 miimind; /* MII management indication reg */
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u32 ifstat; /* Interface Status Register */
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};
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int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
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/* PHY register offsets */
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#define PHY_EXT_PAGE_ACCESS 0x1f
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/* MII Management Configuration Register */
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#define MIIMCFG_RESET_MGMT 0x80000000
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#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
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#define MIIMCFG_INIT_VALUE 0x00000003
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/* MII Management Command Register */
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#define MIIMCOM_READ_CYCLE 0x00000001
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#define MIIMCOM_SCAN_CYCLE 0x00000002
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/* MII Management Address Register */
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#define MIIMADD_PHY_ADDR_SHIFT 8
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/* MII Management Indicator Register */
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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int dev_addr, int reg, int value);
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int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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int dev_addr, int regnum);
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int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
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int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
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u16 value);
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value);
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int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum);
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int memac_mdio_reset(struct mii_dev *bus);
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struct fsl_pq_mdio_info {
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struct tsec_mii_mng __iomem *regs;
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char *name;
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};
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int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
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#endif /* __FSL_PHY_H__ */
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