mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
362 lines
13 KiB
C
362 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*/
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#ifndef _I915_REG_H_
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#define _I915_REG_H_
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/* Hotplug control (945+ only) */
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#define PORT_HOTPLUG_EN 0x61110
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#define HDMIB_HOTPLUG_INT_EN (1 << 29)
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#define DPB_HOTPLUG_INT_EN (1 << 29)
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#define HDMIC_HOTPLUG_INT_EN (1 << 28)
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#define DPC_HOTPLUG_INT_EN (1 << 28)
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#define HDMID_HOTPLUG_INT_EN (1 << 27)
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#define DPD_HOTPLUG_INT_EN (1 << 27)
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#define SDVOB_HOTPLUG_INT_EN (1 << 26)
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#define SDVOC_HOTPLUG_INT_EN (1 << 25)
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#define TV_HOTPLUG_INT_EN (1 << 18)
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#define CRT_HOTPLUG_INT_EN (1 << 9)
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#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
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#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
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/* must use period 64 on GM45 according to docs */
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#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
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#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
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#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
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#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
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#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
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#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
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#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
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#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
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#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
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#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
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#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
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#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
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/* Backlight control */
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#define BLC_PWM_CTL2 0x61250 /* 965+ only */
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#define BLM_PWM_ENABLE (1 << 31)
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#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
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#define BLM_PIPE_SELECT (1 << 29)
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#define BLM_PIPE_SELECT_IVB (3 << 29)
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#define BLM_PIPE_A (0 << 29)
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#define BLM_PIPE_B (1 << 29)
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#define BLM_PIPE_C (2 << 29) /* ivb + */
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#define BLM_PIPE(pipe) ((pipe) << 29)
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#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
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#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
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#define BLM_PHASE_IN_ENABLE (1 << 25)
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#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
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#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
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#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
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#define BLM_PHASE_IN_COUNT_SHIFT (8)
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#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
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#define BLM_PHASE_IN_INCR_SHIFT (0)
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#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
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#define BLC_PWM_CTL 0x61254
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/*
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* This is the most significant 15 bits of the number of backlight cycles in a
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* complete cycle of the modulated backlight control.
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*
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* The actual value is this field multiplied by two.
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*/
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#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
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#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
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#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
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/*
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* This is the number of cycles out of the backlight modulation cycle for which
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* the backlight is on.
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*
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* This field must be no greater than the number of cycles in the complete
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* backlight modulation cycle.
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*/
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#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
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#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
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#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
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#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
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#define BLC_HIST_CTL 0x61260
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/*
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* New registers for PCH-split platforms. Safe where new bits show up, the
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* register layout machtes with gen4 BLC_PWM_CTL[12]
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*/
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#define BLC_PWM_CPU_CTL2 0x48250
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#define BLC_PWM2_ENABLE (1<<31)
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#define BLC_PWM_CPU_CTL 0x48254
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#define BLM_HIST_CTL 0x48260
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#define ENH_HIST_ENABLE (1<<31)
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#define ENH_MODIF_TBL_ENABLE (1<<30)
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#define ENH_PIPE_A_SELECT (0<<29)
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#define ENH_PIPE_B_SELECT (1<<29)
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#define ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
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#define HIST_MODE_YUV (0<<24)
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#define HIST_MODE_HSV (1<<24)
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#define ENH_MODE_DIRECT (0<<13)
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#define ENH_MODE_ADDITIVE (1<<13)
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#define ENH_MODE_MULTIPLICATIVE (2<<13)
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#define BIN_REGISTER_SET (1<<11)
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#define ENH_NUM_BINS 32
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#define BLM_HIST_ENH 0x48264
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#define BLM_HIST_GUARD_BAND 0x48268
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#define BLM_HIST_INTR_ENABLE (1<<31)
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#define BLM_HIST_EVENT_STATUS (1<<30)
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#define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)
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#define BLM_HIST_INTR_DELAY_SHIFT 22
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/*
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* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
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* like the normal CTL from gen4 and earlier. Hooray for confusing naming.
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*/
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#define BLC_PWM_PCH_CTL1 0xc8250
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#define BLM_PCH_PWM_ENABLE (1 << 31)
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#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
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#define BLM_PCH_POLARITY (1 << 29)
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#define BLC_PWM_PCH_CTL2 0xc8254
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/* digital port hotplug */
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#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
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#define PORTD_HOTPLUG_ENABLE (1 << 20)
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#define PORTD_PULSE_DURATION_2ms (0)
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#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
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#define PORTD_PULSE_DURATION_6ms (2 << 18)
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#define PORTD_PULSE_DURATION_100ms (3 << 18)
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#define PORTD_PULSE_DURATION_MASK (3 << 18)
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#define PORTD_HOTPLUG_NO_DETECT (0)
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#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
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#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
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#define PORTC_HOTPLUG_ENABLE (1 << 12)
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#define PORTC_PULSE_DURATION_2ms (0)
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#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
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#define PORTC_PULSE_DURATION_6ms (2 << 10)
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#define PORTC_PULSE_DURATION_100ms (3 << 10)
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#define PORTC_PULSE_DURATION_MASK (3 << 10)
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#define PORTC_HOTPLUG_NO_DETECT (0)
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#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
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#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
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#define PORTB_HOTPLUG_ENABLE (1 << 4)
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#define PORTB_PULSE_DURATION_2ms (0)
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#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
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#define PORTB_PULSE_DURATION_6ms (2 << 2)
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#define PORTB_PULSE_DURATION_100ms (3 << 2)
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#define PORTB_PULSE_DURATION_MASK (3 << 2)
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#define PORTB_HOTPLUG_NO_DETECT (0)
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#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
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#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
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#define PCH_GPIOA 0xc5010
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#define PCH_GPIOB 0xc5014
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#define PCH_GPIOC 0xc5018
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#define PCH_GPIOD 0xc501c
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#define PCH_GPIOE 0xc5020
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#define PCH_GPIOF 0xc5024
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#define PCH_GMBUS0 0xc5100
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#define PCH_GMBUS1 0xc5104
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#define PCH_GMBUS2 0xc5108
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#define PCH_GMBUS3 0xc510c
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#define PCH_GMBUS4 0xc5110
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#define PCH_GMBUS5 0xc5120
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#define _PCH_DPLL_A 0xc6014
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#define _PCH_DPLL_B 0xc6018
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#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
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#define _PCH_FPA0 0xc6040
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#define FP_CB_TUNE (0x3<<22)
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#define _PCH_FPA1 0xc6044
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#define _PCH_FPB0 0xc6048
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#define _PCH_FPB1 0xc604c
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#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
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#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
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#define PCH_DPLL_TEST 0xc606c
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#define PCH_DREF_CONTROL 0xC6200
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#define DREF_CONTROL_MASK 0x7fc3
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#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
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#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
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#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
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#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
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#define DREF_SSC_SOURCE_DISABLE (0<<11)
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#define DREF_SSC_SOURCE_ENABLE (2<<11)
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#define DREF_SSC_SOURCE_MASK (3<<11)
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#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
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#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
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#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
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#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
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#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
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#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
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#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
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#define DREF_SSC4_DOWNSPREAD (0<<6)
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#define DREF_SSC4_CENTERSPREAD (1<<6)
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#define DREF_SSC1_DISABLE (0<<1)
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#define DREF_SSC1_ENABLE (1<<1)
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#define DREF_SSC4_DISABLE (0)
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#define DREF_SSC4_ENABLE (1)
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#define PCH_RAWCLK_FREQ 0xc6204
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#define FDL_TP1_TIMER_SHIFT 12
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#define FDL_TP1_TIMER_MASK (3<<12)
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#define FDL_TP2_TIMER_SHIFT 10
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#define FDL_TP2_TIMER_MASK (3<<10)
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#define RAWCLK_FREQ_MASK 0x3ff
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#define PCH_DPLL_TMR_CFG 0xc6208
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#define PCH_SSC4_PARMS 0xc6210
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#define PCH_SSC4_AUX_PARMS 0xc6214
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#define PCH_DPLL_SEL 0xc7000
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#define TRANSA_DPLL_ENABLE (1<<3)
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#define TRANSA_DPLLB_SEL (1<<0)
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#define TRANSA_DPLLA_SEL 0
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#define TRANSB_DPLL_ENABLE (1<<7)
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#define TRANSB_DPLLB_SEL (1<<4)
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#define TRANSB_DPLLA_SEL (0)
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#define TRANSC_DPLL_ENABLE (1<<11)
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#define TRANSC_DPLLB_SEL (1<<8)
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#define TRANSC_DPLLA_SEL (0)
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/* transcoder */
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#define _TRANS_HTOTAL_A 0xe0000
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#define TRANS_HTOTAL_SHIFT 16
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#define TRANS_HACTIVE_SHIFT 0
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#define _TRANS_HBLANK_A 0xe0004
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#define TRANS_HBLANK_END_SHIFT 16
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#define TRANS_HBLANK_START_SHIFT 0
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#define _TRANS_HSYNC_A 0xe0008
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#define TRANS_HSYNC_END_SHIFT 16
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#define TRANS_HSYNC_START_SHIFT 0
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#define _TRANS_VTOTAL_A 0xe000c
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#define TRANS_VTOTAL_SHIFT 16
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#define TRANS_VACTIVE_SHIFT 0
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#define _TRANS_VBLANK_A 0xe0010
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#define TRANS_VBLANK_END_SHIFT 16
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#define TRANS_VBLANK_START_SHIFT 0
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#define _TRANS_VSYNC_A 0xe0014
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#define TRANS_VSYNC_END_SHIFT 16
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#define TRANS_VSYNC_START_SHIFT 0
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#define _TRANS_VSYNCSHIFT_A 0xe0028
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#define _TRANSA_DATA_M1 0xe0030
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#define _TRANSA_DATA_N1 0xe0034
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#define _TRANSA_DATA_M2 0xe0038
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#define _TRANSA_DATA_N2 0xe003c
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#define _TRANSA_DP_LINK_M1 0xe0040
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#define _TRANSA_DP_LINK_N1 0xe0044
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#define _TRANSA_DP_LINK_M2 0xe0048
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#define _TRANSA_DP_LINK_N2 0xe004c
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/* Per-transcoder DIP controls */
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#define _VIDEO_DIP_CTL_A 0xe0200
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#define _VIDEO_DIP_DATA_A 0xe0208
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#define _VIDEO_DIP_GCP_A 0xe0210
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#define _VIDEO_DIP_CTL_B 0xe1200
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#define _VIDEO_DIP_DATA_B 0xe1208
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#define _VIDEO_DIP_GCP_B 0xe1210
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#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
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#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
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#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
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#define VLV_VIDEO_DIP_CTL_A 0x60200
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#define VLV_VIDEO_DIP_DATA_A 0x60208
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#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
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#define VLV_VIDEO_DIP_CTL_B 0x61170
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#define VLV_VIDEO_DIP_DATA_B 0x61174
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#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
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#define VLV_TVIDEO_DIP_CTL(pipe) \
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_PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
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#define VLV_TVIDEO_DIP_DATA(pipe) \
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_PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
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#define VLV_TVIDEO_DIP_GCP(pipe) \
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_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
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/* vlv has 2 sets of panel control regs. */
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#define PIPEA_PP_STATUS 0x61200
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#define PIPEA_PP_CONTROL 0x61204
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#define PIPEA_PP_ON_DELAYS 0x61208
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#define PIPEA_PP_OFF_DELAYS 0x6120c
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#define PIPEA_PP_DIVISOR 0x61210
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#define PIPEB_PP_STATUS 0x61300
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#define PIPEB_PP_CONTROL 0x61304
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#define PIPEB_PP_ON_DELAYS 0x61308
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#define PIPEB_PP_OFF_DELAYS 0x6130c
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#define PIPEB_PP_DIVISOR 0x61310
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#define PCH_PP_STATUS 0xc7200
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#define PCH_PP_CONTROL 0xc7204
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#define PANEL_UNLOCK_REGS (0xabcd << 16)
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#define PANEL_UNLOCK_MASK (0xffff << 16)
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#define EDP_FORCE_VDD (1 << 3)
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#define EDP_BLC_ENABLE (1 << 2)
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#define PANEL_POWER_RESET (1 << 1)
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#define PANEL_POWER_OFF (0 << 0)
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#define PANEL_POWER_ON (1 << 0)
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#define PCH_PP_ON_DELAYS 0xc7208
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#define PANEL_PORT_SELECT_MASK (3 << 30)
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#define PANEL_PORT_SELECT_LVDS (0 << 30)
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#define PANEL_PORT_SELECT_DPA (1 << 30)
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#define EDP_PANEL (1 << 30)
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#define PANEL_PORT_SELECT_DPC (2 << 30)
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#define PANEL_PORT_SELECT_DPD (3 << 30)
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#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
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#define PANEL_POWER_UP_DELAY_SHIFT 16
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#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
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#define PANEL_LIGHT_ON_DELAY_SHIFT 0
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#define PCH_PP_OFF_DELAYS 0xc720c
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#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
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#define PANEL_POWER_PORT_LVDS (0 << 30)
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#define PANEL_POWER_PORT_DP_A (1 << 30)
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#define PANEL_POWER_PORT_DP_C (2 << 30)
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#define PANEL_POWER_PORT_DP_D (3 << 30)
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#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
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#define PANEL_POWER_DOWN_DELAY_SHIFT 16
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#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
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#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
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#define PCH_PP_DIVISOR 0xc7210
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#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
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#define PP_REFERENCE_DIVIDER_SHIFT 8
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#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
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#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
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#define PCH_DP_B 0xe4100
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#define PCH_DPB_AUX_CH_CTL 0xe4110
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#define PCH_DPB_AUX_CH_DATA1 0xe4114
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#define PCH_DPB_AUX_CH_DATA2 0xe4118
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#define PCH_DPB_AUX_CH_DATA3 0xe411c
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#define PCH_DPB_AUX_CH_DATA4 0xe4120
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#define PCH_DPB_AUX_CH_DATA5 0xe4124
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#define PCH_DP_C 0xe4200
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#define PCH_DPC_AUX_CH_CTL 0xe4210
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#define PCH_DPC_AUX_CH_DATA1 0xe4214
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#define PCH_DPC_AUX_CH_DATA2 0xe4218
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#define PCH_DPC_AUX_CH_DATA3 0xe421c
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#define PCH_DPC_AUX_CH_DATA4 0xe4220
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#define PCH_DPC_AUX_CH_DATA5 0xe4224
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#define PCH_DP_D 0xe4300
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#define PCH_DPD_AUX_CH_CTL 0xe4310
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#define PCH_DPD_AUX_CH_DATA1 0xe4314
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#define PCH_DPD_AUX_CH_DATA2 0xe4318
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#define PCH_DPD_AUX_CH_DATA3 0xe431c
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#define PCH_DPD_AUX_CH_DATA4 0xe4320
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#define PCH_DPD_AUX_CH_DATA5 0xe4324
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#endif /* _I915_REG_H_ */
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