mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
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*/
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/* Registers at i2c address 0x38 */
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#define ANX9804_HDCP_CONTROL_0_REG 0x01
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#define ANX9804_SYS_CTRL1_REG 0x80
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#define ANX9804_SYS_CTRL1_PD_IO 0x80
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#define ANX9804_SYS_CTRL1_PD_VID 0x40
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#define ANX9804_SYS_CTRL1_PD_LINK 0x20
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#define ANX9804_SYS_CTRL1_PD_TOTAL 0x10
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#define ANX9804_SYS_CTRL1_MODE_SEL 0x08
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#define ANX9804_SYS_CTRL1_DET_STA 0x04
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#define ANX9804_SYS_CTRL1_FORCE_DET 0x02
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#define ANX9804_SYS_CTRL1_DET_CTRL 0x01
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#define ANX9804_SYS_CTRL2_REG 0x81
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#define ANX9804_SYS_CTRL2_CHA_STA 0x04
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#define ANX9804_SYS_CTRL3_REG 0x82
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#define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0)
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#define ANX9804_SYS_CTRL3_F_VALID BIT(1)
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#define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4)
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#define ANX9804_SYS_CTRL3_F_HPD BIT(5)
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#define ANX9804_LINK_BW_SET_REG 0xa0
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#define ANX9804_LANE_COUNT_SET_REG 0xa1
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#define ANX9804_TRAINING_PTN_SET_REG 0xa2
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#define ANX9804_TRAINING_LANE0_SET_REG 0xa3
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#define ANX9804_TRAINING_LANE1_SET_REG 0xa4
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#define ANX9804_TRAINING_LANE2_SET_REG 0xa5
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#define ANX9804_TRAINING_LANE3_SET_REG 0xa6
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#define ANX9804_LINK_TRAINING_CTRL_REG 0xa8
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#define ANX9804_LINK_TRAINING_CTRL_EN BIT(0)
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#define ANX9804_LINK_DEBUG_REG 0xb8
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#define ANX9804_PLL_CTRL_REG 0xc7
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#define ANX9804_ANALOG_POWER_DOWN_REG 0xc8
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#define ANX9804_AUX_CH_STA 0xe0
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#define ANX9804_AUX_BUSY BIT(4)
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#define ANX9804_AUX_STATUS_MASK 0x0f
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#define ANX9804_DP_AUX_RX_COMM 0xe3
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#define ANX9804_AUX_RX_COMM_I2C_DEFER BIT(3)
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#define ANX9804_AUX_RX_COMM_AUX_DEFER BIT(1)
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#define ANX9804_DP_AUX_CH_CTL_1 0xe5
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#define ANX9804_AUX_LENGTH(x) (((x - 1) & 0x0f) << 4)
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#define ANX9804_AUX_TX_COMM_MASK 0x0f
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#define ANX9804_AUX_TX_COMM_DP_TRANSACTION BIT(3)
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#define ANX9804_AUX_TX_COMM_MOT BIT(2)
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#define ANX9804_AUX_TX_COMM_READ BIT(0)
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#define ANX9804_DP_AUX_ADDR_7_0 0xe6
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#define ANX9804_DP_AUX_ADDR_15_8 0xe7
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#define ANX9804_DP_AUX_ADDR_19_16 0xe8
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#define ANX9804_DP_AUX_CH_CTL_2 0xe9
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#define ANX9804_ADDR_ONLY BIT(1)
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#define ANX9804_AUX_EN BIT(0)
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#define ANX9804_BUF_DATA_0 0xf0
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/* Registers at i2c address 0x39 */
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#define ANX9804_DEV_IDH_REG 0x03
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#define ANX9804_POWERD_CTRL_REG 0x05
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#define ANX9804_POWERD_AUDIO BIT(4)
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#define ANX9804_RST_CTRL_REG 0x06
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#define ANX9804_RST_CTRL2_REG 0x07
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#define ANX9804_RST_CTRL2_AUX BIT(2)
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#define ANX9804_RST_CTRL2_AC_MODE BIT(6)
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#define ANX9804_VID_CTRL1_REG 0x08
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#define ANX9804_VID_CTRL1_VID_EN BIT(7)
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#define ANX9804_VID_CTRL1_EDGE BIT(0)
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#define ANX9804_VID_CTRL2_REG 0x09
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#define ANX9804_ANALOG_DEBUG_REG1 0xdc
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#define ANX9804_ANALOG_DEBUG_REG3 0xde
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#define ANX9804_PLL_FILTER_CTRL1 0xdf
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#define ANX9804_PLL_FILTER_CTRL3 0xe1
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#define ANX9804_PLL_FILTER_CTRL 0xe2
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#define ANX9804_PLL_CTRL3 0xe6
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#define ANX9804_DP_INT_STA 0xf7
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#define ANX9804_RPLY_RECEIV BIT(1)
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#define ANX9804_AUX_ERR BIT(0)
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