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https://github.com/brain-hackers/u-boot-brain
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739ba41d5a
The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Socionext Inc.
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*/
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#include <linux/delay.h>
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#include "../init.h"
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#include "../sc64-regs.h"
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#include "pll.h"
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/* PLL type: SSC */
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#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
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#define SC_SPLLCTRL 0x1410 /* misc */
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#define SC_SPLL2CTRL 0x1420 /* DSP */
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#define SC_VPPLLCTRL 0x1430 /* VPE */
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#define SC_VGPLLCTRL 0x1440
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#define SC_DECPLLCTRL 0x1450
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#define SC_ENCPLLCTRL 0x1460
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#define SC_PXFPLLCTRL 0x1470
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#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */
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#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */
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#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */
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#define SC_VSPLLCTRL 0x14c0
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/* PLL type: VPLL27 */
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#define SC_VPLL27FCTRL 0x1500
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#define SC_VPLL27ACTRL 0x1520
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/* PLL type: DSPLL */
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#define SC_VPLL8KCTRL 0x1540
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void uniphier_pxs3_pll_init(void)
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{
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uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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/* do nothing for SPLL */
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uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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mdelay(1);
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uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
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uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
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}
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