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5bacb4402e
Now that the reset controlling of the Denali NAND driver (denali_dt.c) works for this platform, remove the adhoc reset deassert code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
40 lines
976 B
C
40 lines
976 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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void uniphier_pxs2_clk_init(void)
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{
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#ifdef CONFIG_USB_DWC3_UNIPHIER
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u32 tmp;
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/* deassert reset */
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tmp = readl(sc_base + SC_RSTCTRL);
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tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
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writel(tmp, sc_base + SC_RSTCTRL);
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readl(sc_base + SC_RSTCTRL); /* dummy read */
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tmp = readl(sc_base + SC_RSTCTRL2);
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tmp |= SC_RSTCTRL2_NRST_USB3B1;
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writel(tmp, sc_base + SC_RSTCTRL2);
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readl(sc_base + SC_RSTCTRL2); /* dummy read */
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tmp = readl(sc_base + SC_RSTCTRL6);
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tmp |= 0x37;
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writel(tmp, sc_base + SC_RSTCTRL6);
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/* provide clocks */
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tmp = readl(sc_base + SC_CLKCTRL);
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tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
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SC_CLKCTRL_CEN_GIO;
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writel(tmp, sc_base + SC_CLKCTRL);
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readl(sc_base + SC_CLKCTRL); /* dummy read */
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#endif
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}
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