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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
12ffe75819
Modify dts files to add 'no-1-8-v' property for all the ZynqMP boards. User can remove this property to enable the UHS mode. This is to keep the same speed (HS) modes across all the stages of the Linux Boot. Due to power cycling limitation of some of the ZynqMP boards, some SD cards don't get power cycled and are failing in Linux. Signed-off-by: Manish Narani <manish.narani@xilinx.com>
250 lines
4.7 KiB
Plaintext
250 lines
4.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP ZCU1285 RevA
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*
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* (C) Copyright 2018 - 2020, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP ZCU1285 RevA";
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compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
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"xlnx,zynqmp";
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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mmc0 = &sdhci1;
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i2c = &i2c0; /* EMIO */
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ina226-u60 {
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compatible = "iio-hwmon";
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io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
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};
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ina226-u61 {
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compatible = "iio-hwmon";
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io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
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};
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ina226-u63 {
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compatible = "iio-hwmon";
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io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
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};
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ina226-u65 {
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compatible = "iio-hwmon";
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io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
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};
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ina226-u64 {
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compatible = "iio-hwmon";
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io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
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};
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};
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&dcc {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@75 {
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compatible = "nxp,pca9548"; /* u22 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PMBUS */
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max20751@74 { /* u23 */
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compatible = "maxim,max20751";
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reg = <0x74>;
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};
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max20751@70 { /* u89 */
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compatible = "maxim,max20751";
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reg = <0x70>;
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};
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max15301@a { /* u28 */
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compatible = "maxim,max15301";
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reg = <0xa>;
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};
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max15303@b { /* u48 */
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compatible = "maxim,max15303";
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reg = <0xb>;
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};
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max15303@d { /* u27 */
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compatible = "maxim,max15303";
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reg = <0xd>;
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};
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max15303@e { /* u11 */
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compatible = "maxim,max15303";
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reg = <0xe>;
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};
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max15303@f { /* u96 */
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compatible = "maxim,max15303";
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reg = <0xf>;
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};
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max15303@11 { /* u47 */
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compatible = "maxim,max15303";
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reg = <0x11>;
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};
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max15303@12 { /* u24 */
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compatible = "maxim,max15303";
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reg = <0x12>;
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};
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max15301@13 { /* u29 */
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compatible = "maxim,max15301";
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reg = <0x13>;
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};
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max15303@14 { /* u51 */
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compatible = "maxim,max15303";
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reg = <0x14>;
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};
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max15303@15 { /* u30 */
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compatible = "maxim,max15303";
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reg = <0x15>;
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};
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max15303@16 { /* u102 */
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compatible = "maxim,max15303";
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reg = <0x16>;
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};
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max15301@17 { /* u50 */
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compatible = "maxim,max15301";
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reg = <0x17>;
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};
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max15301@18 { /* u31 */
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compatible = "maxim,max15301";
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reg = <0x18>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* CM_I2C */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* SYS_EEPROM */
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eeprom: eeprom@54 { /* u101 */
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compatible = "atmel,24c32"; /* 24LC32A */
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reg = <0x54>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* FMC1 */
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* FMC2 */
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* ANALOG_PMBUS */
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u60: ina226@40 { /* u60 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u60";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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u61: ina226@41 { /* u61 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u61";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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u63: ina226@42 { /* u63 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u63";
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reg = <0x42>;
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shunt-resistor = <1000>;
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};
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u65: ina226@43 { /* u65 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u65";
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reg = <0x43>;
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shunt-resistor = <1000>;
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};
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u64: ina226@44 { /* u64 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u64";
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reg = <0x44>;
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shunt-resistor = <1000>;
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};
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* ANALOG_CM_I2C */
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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/* FMC3 */
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};
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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};
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};
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&uart0 {
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status = "okay";
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};
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&sdhci1 {
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status = "okay";
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/*
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* This property should be removed for supporting UHS mode
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*/
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no-1-8-v;
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xlnx,mio_bank = <1>;
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};
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