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https://github.com/brain-hackers/u-boot-brain
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Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB), USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each). Boards have mix of Winbond/ST QSPIs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
104 lines
1.7 KiB
Plaintext
104 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Zynq DLC20 Rev1.0";
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compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20",
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"xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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serial0 = &uart1;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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chosen {
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0@e0002000 {
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compatible = "ulpi-phy";
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#phy-cells = <0>;
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reg = <0xe0002000 0x1000>;
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view-port = <0x0170>;
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drv-vbus;
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>; /* U7 */
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};
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&gem0 {
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status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */
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reg = <1>;
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};
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};
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&i2c0 {
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status = "okay"; /* MIO14/15 */
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clock-frequency = <400000>;
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/* U46 - m24c08 */
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eeprom: eeprom@54 {
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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};
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&qspi {
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u-boot,dm-pre-reloc;
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status = "okay";
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is-dual = <0>;
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num-cs = <1>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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flash@0 {
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/* Rev1.0 W25Q128FWSIG, RevC N25Q128A */
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compatible = "n25q128a11", "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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};
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};
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&sdhci0 {
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u-boot,dm-pre-reloc;
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status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */
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non-removable;
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bus-width = <4>;
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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status = "okay"; /* MIO8/9 */
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};
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&usb0 {
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status = "okay"; /* MIO28-MIO39 */
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dr_mode = "device";
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usb-phy = <&usb_phy0>;
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};
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&watchdog0 {
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reset-on-timeout;
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};
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