mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1b28a5e2b0
DT alignment with Linux 5.7-rc2, including the kernel commits 431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards 79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards 877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards 7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1 d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c 1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1 bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1 b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards 8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1 fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151 c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1 9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15 82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151 8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1 4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1 80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1 ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
*/
|
|
|
|
#include "stm32mp151.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a7";
|
|
clock-frequency = <650000000>;
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
m_can1: can@4400e000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
m_can2: can@4400f000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|