mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
3958ef307e
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
143 lines
1.6 KiB
Plaintext
143 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014, 2020, Intel Corporation
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*/
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/ {
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chosen {
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tick-timer = &timer2;
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u-boot,dm-pre-reloc;
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};
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memory@0 {
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&clkmgr {
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u-boot,dm-pre-reloc;
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clocks {
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u-boot,dm-pre-reloc;
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};
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};
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&cb_intosc_hs_div2_clk {
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u-boot,dm-pre-reloc;
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};
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&cb_intosc_ls_clk {
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u-boot,dm-pre-reloc;
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};
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&f2s_free_clk {
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u-boot,dm-pre-reloc;
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};
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&gmac0 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x44 0>;
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};
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&gmac1 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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};
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&gmac2 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
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};
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&i2c0 {
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reset-names = "i2c";
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};
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&i2c1 {
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reset-names = "i2c";
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};
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&i2c2 {
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reset-names = "i2c";
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};
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&i2c3 {
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reset-names = "i2c";
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};
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&i2c4 {
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reset-names = "i2c";
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};
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&L2 {
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u-boot,dm-pre-reloc;
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};
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&l4_mp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sys_free_clk {
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u-boot,dm-pre-reloc;
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};
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&main_periph_ref_clk {
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u-boot,dm-pre-reloc;
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};
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&main_pll {
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u-boot,dm-pre-reloc;
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};
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&main_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&noc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&osc1 {
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u-boot,dm-pre-reloc;
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};
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&peri_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&periph_pll {
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u-boot,dm-pre-reloc;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&portc {
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bank-name = "portc";
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};
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&rst {
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u-boot,dm-pre-reloc;
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};
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&sysmgr {
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u-boot,dm-pre-reloc;
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};
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&timer2 {
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u-boot,dm-pre-reloc;
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};
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