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https://github.com/brain-hackers/u-boot-brain
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fb3862823b
Add device tree files for Agilex SoC platform. socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains Uboot specific DT properties. socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
97 lines
1.2 KiB
Plaintext
97 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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/{
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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ccu: cache-controller@f7000000 {
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compatible = "arteris,ncore-ccu";
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reg = <0xf7000000 0x100900>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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&clkmgr {
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u-boot,dm-pre-reloc;
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};
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&gmac1 {
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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};
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&gmac2 {
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altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
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};
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&i2c0 {
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reset-names = "i2c";
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};
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&i2c1 {
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reset-names = "i2c";
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};
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&i2c2 {
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reset-names = "i2c";
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};
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&i2c3 {
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reset-names = "i2c";
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};
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&mmc {
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resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&qspi {
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u-boot,dm-pre-reloc;
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};
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&rst {
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compatible = "altr,rst-mgr";
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altr,modrst-offset = <0x20>;
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u-boot,dm-pre-reloc;
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};
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&sdr {
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compatible = "intel,sdr-ctl-agilex";
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reg = <0xf8000400 0x80>,
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<0xf8010000 0x190>,
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<0xf8011000 0x500>;
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resets = <&rst DDRSCH_RESET>;
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u-boot,dm-pre-reloc;
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};
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&sysmgr {
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compatible = "altr,sys-mgr", "syscon";
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&watchdog0 {
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u-boot,dm-pre-reloc;
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};
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