79 lines
1.7 KiB
Plaintext
79 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
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*
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
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*/
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#include "sama5d2.dtsi"
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#include "sama5d2-pinfunc.h"
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/ {
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model = "Microchip SAMA5D27 WLSOM1";
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compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
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memory {
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reg = <0x20000000 0x10000000>;
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};
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ahb {
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apb {
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qspi1: spi@f0024000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi1_default>;
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qspi1_flash: spi_flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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macb0: ethernet@f8008000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
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phy-mode = "rmii";
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ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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pioA: gpio@fc038000 {
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pinctrl {
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pinctrl_macb0_phy_irq: macb0_phy_irq {
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pinmux = <PIN_PB24__GPIO>;
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bias-disable;
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};
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pinctrl_macb0_rmii: macb0_rmii {
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pinmux = <PIN_PB14__GTXCK>,
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<PIN_PB15__GTXEN>,
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<PIN_PB16__GRXDV>,
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<PIN_PB17__GRXER>,
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<PIN_PB18__GRX0>,
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<PIN_PB19__GRX1>,
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<PIN_PB20__GTX0>,
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<PIN_PB21__GTX1>,
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<PIN_PB22__GMDC>,
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<PIN_PB23__GMDIO>;
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bias-disable;
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};
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pinctrl_qspi1_default: qspi1_default {
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pinmux = <PIN_PB5__QSPI1_SCK>,
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<PIN_PB6__QSPI1_CS>,
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<PIN_PB7__QSPI1_IO0>,
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<PIN_PB8__QSPI1_IO1>,
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<PIN_PB9__QSPI1_IO2>,
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<PIN_PB10__QSPI1_IO3>;
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bias-pull-up;
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};
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};
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};
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};
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};
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};
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