mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
228f9e0244
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Enable the qspi node together with the SST26VF064B qspi nor flash memory. Booting from the QSPI NOR flash is now possible. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
133 lines
1.3 KiB
Plaintext
133 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
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*
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
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*/
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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pinctrl {
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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&sdhci0 {
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u-boot,dm-pre-reloc;
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};
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&dbgu {
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u-boot,dm-pre-reloc;
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};
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&qspi {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_dbgu {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_sdhci0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_qspi {
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u-boot,dm-pre-reloc;
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};
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&pioA {
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u-boot,dm-pre-reloc;
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};
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&pioB {
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u-boot,dm-pre-reloc;
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};
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&pmc {
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u-boot,dm-pre-reloc;
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};
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&main {
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u-boot,dm-pre-reloc;
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};
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&plla {
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u-boot,dm-pre-reloc;
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};
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&mck {
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u-boot,dm-pre-reloc;
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};
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&system {
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u-boot,dm-pre-reloc;
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};
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&qspick {
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u-boot,dm-pre-reloc;
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};
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&periph {
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u-boot,dm-pre-reloc;
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};
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&pioA_clk {
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u-boot,dm-pre-reloc;
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};
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&pioB_clk {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_clk {
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u-boot,dm-pre-reloc;
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};
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&dbgu_clk {
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u-boot,dm-pre-reloc;
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};
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&qspi_clk {
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u-boot,dm-pre-reloc;
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};
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&generic {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_gclk {
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u-boot,dm-pre-reloc;
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};
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&slowckc {
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u-boot,dm-pre-reloc;
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};
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&slow_osc {
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u-boot,dm-pre-reloc;
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};
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&slow_rc_osc {
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u-boot,dm-pre-reloc;
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};
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&td_slck {
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u-boot,dm-pre-reloc;
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};
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&md_slck {
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u-boot,dm-pre-reloc;
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};
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