261 lines
6.6 KiB
Plaintext
261 lines
6.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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/dts-v1/;
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#include "imxrt1050.dtsi"
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#include "imxrt1050-evk-u-boot.dtsi"
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#include <dt-bindings/pinctrl/pins-imxrt1050.h>
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/ {
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model = "NXP IMXRT1050-evk board";
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compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
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chosen {
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bootargs = "root=/dev/ram";
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0x80000000 0x2000000>;
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};
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};
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&lpuart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&semc {
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/*
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* Memory configuration from sdram datasheet IS42S16160J-6BLI
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*/
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fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
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MUX_CSX0_SDRAM_CS1
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0
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0
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0
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0>;
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fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
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BL_8
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COL_9BITS
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CL_3>;
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fsl,sdram-timing = /bits/ 8 <0x2
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0x2
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0x9
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0x1
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0x5
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0x6
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0x20
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0x09
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0x01
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0x00
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0x04
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0x0A
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0x21
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0x50>;
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bank1: bank@0 {
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fsl,base-address = <0x80000000>;
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fsl,memory-size = <MEM_SIZE_32M>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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imxrt1050-evk {
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
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0xf1
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MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
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0xf1
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>;
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};
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pinctrl_semc: semcgrp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
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0xf1 /* SEMC_D0 */
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MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
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0xf1 /* SEMC_D1 */
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MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
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0xf1 /* SEMC_D2 */
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MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
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0xf1 /* SEMC_D3 */
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MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
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0xf1 /* SEMC_D4 */
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MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
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0xf1 /* SEMC_D5 */
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MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
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0xf1 /* SEMC_D6 */
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MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
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0xf1 /* SEMC_D7 */
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MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
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0xf1 /* SEMC_DM0 */
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MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
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0xf1 /* SEMC_A0 */
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MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
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0xf1 /* SEMC_A1 */
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MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
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0xf1 /* SEMC_A2 */
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MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
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0xf1 /* SEMC_A3 */
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MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
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0xf1 /* SEMC_A4 */
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MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
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0xf1 /* SEMC_A5 */
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MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
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0xf1 /* SEMC_A6 */
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MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
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0xf1 /* SEMC_A7 */
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MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
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0xf1 /* SEMC_A8 */
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MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
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0xf1 /* SEMC_A9 */
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MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
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0xf1 /* SEMC_A11 */
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MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
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0xf1 /* SEMC_A12 */
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MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
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0xf1 /* SEMC_BA0 */
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MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
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0xf1 /* SEMC_BA1 */
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MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
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0xf1 /* SEMC_A10 */
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MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
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0xf1 /* SEMC_CAS */
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MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
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0xf1 /* SEMC_RAS */
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MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
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0xf1 /* SEMC_CLK */
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MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
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0xf1 /* SEMC_CKE */
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MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
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0xf1 /* SEMC_WE */
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MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
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0xf1 /* SEMC_CS0 */
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MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
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0xf1 /* SEMC_D8 */
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MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
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0xf1 /* SEMC_D9 */
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MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
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0xf1 /* SEMC_D10 */
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MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
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0xf1 /* SEMC_D11 */
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MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
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0xf1 /* SEMC_D12 */
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MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
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0xf1 /* SEMC_D13 */
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MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
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0xf1 /* SEMC_D14 */
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MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
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0xf1 /* SEMC_D15 */
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MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
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0xf1 /* SEMC_DM1 */
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MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
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(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
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0x1B000
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MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
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0xB069
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MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
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0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
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0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
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0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
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0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
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0x17061
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MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
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0x17061
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>;
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};
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pinctrl_lcdif: lcdifgrp {
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u-boot,dm-spl;
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
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MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
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>;
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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pinctrl-3 = <&pinctrl_usdhc0>;
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status = "okay";
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cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif>;
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display = <&display0>;
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status = "okay";
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assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
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assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
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display0: display0 {
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bits-per-pixel = <16>;
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bus-width = <16>;
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display-timings {
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timing0: timing0 {
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clock-frequency = <9300000>;
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hactive = <480>;
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vactive = <272>;
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hback-porch = <4>;
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hfront-porch = <8>;
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vback-porch = <4>;
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vfront-porch = <8>;
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hsync-len = <41>;
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vsync-len = <10>;
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de-active = <1>;
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pixelclk-active = <0>;
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hsync-active = <0>;
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vsync-active = <0>;
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};
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};
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};
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};
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