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![Joe Hershberger](/assets/img/avatar_default.png)
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
965 lines
23 KiB
C
965 lines
23 KiB
C
/*
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* (C) Copyright 2010
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* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
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* Martin Krause, Martin.Krause@tqs.de
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* reworked original enc28j60.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <net.h>
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#include <spi.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include "enc28j60.h"
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/*
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* IMPORTANT: spi_claim_bus() and spi_release_bus()
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* are called at begin and end of each of the following functions:
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* enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
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* enc_init(), enc_recv(), enc_send(), enc_halt()
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* ALL other functions assume that the bus has already been claimed!
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* Since net_process_received_packet() might call enc_send() in return, the bus
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* must be released, net_process_received_packet() called and claimed again.
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*/
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/*
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* Controller memory layout.
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* We only allow 1 frame for transmission and reserve the rest
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* for reception to handle as many broadcast packets as possible.
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* Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
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* 0x0000 - 0x19ff 6656 bytes receive buffer
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* 0x1a00 - 0x1fff 1536 bytes transmit buffer =
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* control(1)+frame(1518)+status(7)+reserve(10).
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*/
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#define ENC_RX_BUF_START 0x0000
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#define ENC_RX_BUF_END 0x19ff
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#define ENC_TX_BUF_START 0x1a00
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#define ENC_TX_BUF_END 0x1fff
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#define ENC_MAX_FRM_LEN 1518
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#define RX_RESET_COUNTER 1000
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/*
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* For non data transfer functions, like phy read/write, set hwaddr, init
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* we do not need a full, time consuming init including link ready wait.
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* This enum helps to bring the chip through the minimum necessary inits.
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*/
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enum enc_initstate {none=0, setupdone, linkready};
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typedef struct enc_device {
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struct eth_device *dev; /* back pointer */
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struct spi_slave *slave;
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int rx_reset_counter;
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u16 next_pointer;
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u8 bank; /* current bank in enc28j60 */
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enum enc_initstate initstate;
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} enc_dev_t;
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/*
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* enc_bset: set bits in a common register
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* enc_bclr: clear bits in a common register
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*
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* making the reg parameter u8 will give a compile time warning if the
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* functions are called with a register not accessible in all Banks
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*/
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static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
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{
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u8 dout[2];
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dout[0] = CMD_BFS(reg);
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dout[1] = data;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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}
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static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
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{
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u8 dout[2];
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dout[0] = CMD_BFC(reg);
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dout[1] = data;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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}
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/*
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* high byte of the register contains bank number:
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* 0: no bank switch necessary
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* 1: switch to bank 0
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* 2: switch to bank 1
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* 3: switch to bank 2
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* 4: switch to bank 3
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*/
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static void enc_set_bank(enc_dev_t *enc, const u16 reg)
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{
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u8 newbank = reg >> 8;
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if (newbank == 0 || newbank == enc->bank)
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return;
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switch (newbank) {
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case 1:
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enc_bclr(enc, CTL_REG_ECON1,
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ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
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break;
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case 2:
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enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
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enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
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break;
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case 3:
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enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
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enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
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break;
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case 4:
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enc_bset(enc, CTL_REG_ECON1,
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ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
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break;
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}
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enc->bank = newbank;
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}
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/*
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* local functions to access SPI
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*
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* reg: register inside ENC28J60
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* data: 8/16 bits to write
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* c: number of retries
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*
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* enc_r8: read 8 bits
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* enc_r16: read 16 bits
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* enc_w8: write 8 bits
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* enc_w16: write 16 bits
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* enc_w8_retry: write 8 bits, verify and retry
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* enc_rbuf: read from ENC28J60 into buffer
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* enc_wbuf: write from buffer into ENC28J60
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*/
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/*
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* MAC and MII registers need a 3 byte SPI transfer to read,
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* all other registers need a 2 byte SPI transfer.
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*/
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static int enc_reg2nbytes(const u16 reg)
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{
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/* check if MAC or MII register */
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return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
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(reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
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(reg == CTL_REG_MISTAT)) ? 3 : 2;
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}
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/*
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* Read a byte register
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*/
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static u8 enc_r8(enc_dev_t *enc, const u16 reg)
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{
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u8 dout[3];
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u8 din[3];
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int nbytes = enc_reg2nbytes(reg);
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enc_set_bank(enc, reg);
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dout[0] = CMD_RCR(reg);
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spi_xfer(enc->slave, nbytes * 8, dout, din,
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SPI_XFER_BEGIN | SPI_XFER_END);
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return din[nbytes-1];
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}
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/*
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* Read a L/H register pair and return a word.
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* Must be called with the L register's address.
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*/
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static u16 enc_r16(enc_dev_t *enc, const u16 reg)
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{
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u8 dout[3];
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u8 din[3];
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u16 result;
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int nbytes = enc_reg2nbytes(reg);
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enc_set_bank(enc, reg);
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dout[0] = CMD_RCR(reg);
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spi_xfer(enc->slave, nbytes * 8, dout, din,
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SPI_XFER_BEGIN | SPI_XFER_END);
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result = din[nbytes-1];
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dout[0]++; /* next register */
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spi_xfer(enc->slave, nbytes * 8, dout, din,
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SPI_XFER_BEGIN | SPI_XFER_END);
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result |= din[nbytes-1] << 8;
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return result;
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}
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/*
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* Write a byte register
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*/
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static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
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{
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u8 dout[2];
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enc_set_bank(enc, reg);
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dout[0] = CMD_WCR(reg);
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dout[1] = data;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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}
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/*
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* Write a L/H register pair.
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* Must be called with the L register's address.
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*/
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static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
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{
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u8 dout[2];
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enc_set_bank(enc, reg);
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dout[0] = CMD_WCR(reg);
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dout[1] = data;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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dout[0]++; /* next register */
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dout[1] = data >> 8;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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}
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/*
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* Write a byte register, verify and retry
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*/
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static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
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{
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u8 dout[2];
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u8 readback;
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int i;
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enc_set_bank(enc, reg);
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for (i = 0; i < c; i++) {
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dout[0] = CMD_WCR(reg);
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dout[1] = data;
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spi_xfer(enc->slave, 2 * 8, dout, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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readback = enc_r8(enc, reg);
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if (readback == data)
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break;
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/* wait 1ms */
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udelay(1000);
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}
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if (i == c) {
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printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
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}
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}
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/*
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* Read ENC RAM into buffer
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*/
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static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
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{
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u8 dout[1];
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dout[0] = CMD_RBM;
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spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
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spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
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#ifdef DEBUG
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puts("Rx:\n");
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print_buffer(0, buf, 1, length, 0);
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#endif
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}
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/*
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* Write buffer into ENC RAM
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*/
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static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
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{
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u8 dout[2];
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dout[0] = CMD_WBM;
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dout[1] = control;
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spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
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spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
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#ifdef DEBUG
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puts("Tx:\n");
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print_buffer(0, buf, 1, length, 0);
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#endif
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}
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/*
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* Try to claim the SPI bus.
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* Print error message on failure.
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*/
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static int enc_claim_bus(enc_dev_t *enc)
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{
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int rc = spi_claim_bus(enc->slave);
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if (rc)
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printf("%s: failed to claim SPI bus\n", enc->dev->name);
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return rc;
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}
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/*
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* Release previously claimed SPI bus.
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* This function is mainly for symmetry to enc_claim_bus().
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* Let the toolchain decide to inline it...
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*/
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static void enc_release_bus(enc_dev_t *enc)
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{
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spi_release_bus(enc->slave);
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}
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/*
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* Read PHY register
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*/
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static u16 enc_phy_read(enc_dev_t *enc, const u8 addr)
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{
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uint64_t etime;
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u8 status;
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enc_w8(enc, CTL_REG_MIREGADR, addr);
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enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
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/* 1 second timeout - only happens on hardware problem */
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etime = get_ticks() + get_tbclk();
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/* poll MISTAT.BUSY bit until operation is complete */
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do
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{
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status = enc_r8(enc, CTL_REG_MISTAT);
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} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
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if (status & ENC_MISTAT_BUSY) {
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printf("%s: timeout reading phy\n", enc->dev->name);
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return 0;
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}
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enc_w8(enc, CTL_REG_MICMD, 0);
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return enc_r16(enc, CTL_REG_MIRDL);
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}
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/*
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* Write PHY register
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*/
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static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
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{
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uint64_t etime;
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u8 status;
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enc_w8(enc, CTL_REG_MIREGADR, addr);
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enc_w16(enc, CTL_REG_MIWRL, data);
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/* 1 second timeout - only happens on hardware problem */
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etime = get_ticks() + get_tbclk();
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/* poll MISTAT.BUSY bit until operation is complete */
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do
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{
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status = enc_r8(enc, CTL_REG_MISTAT);
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} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
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if (status & ENC_MISTAT_BUSY) {
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printf("%s: timeout writing phy\n", enc->dev->name);
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return;
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}
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}
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/*
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* Verify link status, wait if necessary
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*
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* Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
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* half/full duplex is a pure setup matter. For the time being, this driver
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* will setup in half duplex mode only.
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*/
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static int enc_phy_link_wait(enc_dev_t *enc)
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{
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u16 status;
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int duplex;
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uint64_t etime;
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#ifdef CONFIG_ENC_SILENTLINK
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/* check if we have a link, then just return */
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status = enc_phy_read(enc, PHY_REG_PHSTAT1);
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if (status & ENC_PHSTAT1_LLSTAT)
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return 0;
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#endif
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/* wait for link with 1 second timeout */
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etime = get_ticks() + get_tbclk();
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while (get_ticks() <= etime) {
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status = enc_phy_read(enc, PHY_REG_PHSTAT1);
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if (status & ENC_PHSTAT1_LLSTAT) {
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/* now we have a link */
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status = enc_phy_read(enc, PHY_REG_PHSTAT2);
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duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
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printf("%s: link up, 10Mbps %s-duplex\n",
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enc->dev->name, duplex ? "full" : "half");
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return 0;
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}
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udelay(1000);
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}
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/* timeout occured */
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printf("%s: link down\n", enc->dev->name);
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return 1;
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}
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/*
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* This function resets the receiver only.
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*/
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static void enc_reset_rx(enc_dev_t *enc)
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{
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u8 econ1;
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econ1 = enc_r8(enc, CTL_REG_ECON1);
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if ((econ1 & ENC_ECON1_RXRST) == 0) {
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enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
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enc->rx_reset_counter = RX_RESET_COUNTER;
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}
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}
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/*
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* Reset receiver and reenable it.
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*/
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static void enc_reset_rx_call(enc_dev_t *enc)
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{
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enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
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enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
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}
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/*
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* Copy a packet from the receive ring and forward it to
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* the protocol stack.
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*/
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static void enc_receive(enc_dev_t *enc)
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{
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u8 *packet = (u8 *)net_rx_packets[0];
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u16 pkt_len;
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u16 copy_len;
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u16 status;
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u8 pkt_cnt = 0;
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u16 rxbuf_rdpt;
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u8 hbuf[6];
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enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
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do {
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enc_rbuf(enc, 6, hbuf);
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enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
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pkt_len = hbuf[2] | (hbuf[3] << 8);
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status = hbuf[4] | (hbuf[5] << 8);
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debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
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enc->next_pointer, pkt_len, status);
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if (pkt_len <= ENC_MAX_FRM_LEN)
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copy_len = pkt_len;
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else
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copy_len = 0;
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if ((status & (1L << 7)) == 0) /* check Received Ok bit */
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copy_len = 0;
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/* check if next pointer is resonable */
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if (enc->next_pointer >= ENC_TX_BUF_START)
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copy_len = 0;
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if (copy_len > 0) {
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enc_rbuf(enc, copy_len, packet);
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}
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/* advance read pointer to next pointer */
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enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
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/* decrease packet counter */
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enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
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/*
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* Only odd values should be written to ERXRDPTL,
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* see errata B4 pt.13
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*/
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rxbuf_rdpt = enc->next_pointer - 1;
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if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
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(rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
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enc_w16(enc, CTL_REG_ERXRDPTL,
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enc_r16(enc, CTL_REG_ERXNDL));
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} else {
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enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
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}
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/* read pktcnt */
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pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
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if (copy_len == 0) {
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(void)enc_r8(enc, CTL_REG_EIR);
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enc_reset_rx(enc);
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printf("%s: receive copy_len=0\n", enc->dev->name);
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continue;
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}
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/*
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* Because net_process_received_packet() might call enc_send(),
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* we need to release the SPI bus, call
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* net_process_received_packet(), reclaim the bus.
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*/
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enc_release_bus(enc);
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net_process_received_packet(packet, pkt_len);
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if (enc_claim_bus(enc))
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return;
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(void)enc_r8(enc, CTL_REG_EIR);
|
|
} while (pkt_cnt);
|
|
/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
|
}
|
|
|
|
/*
|
|
* Poll for completely received packets.
|
|
*/
|
|
static void enc_poll(enc_dev_t *enc)
|
|
{
|
|
u8 eir_reg;
|
|
u8 pkt_cnt;
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
/* clear global interrupt enable bit in enc28j60 */
|
|
enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
|
|
#endif
|
|
(void)enc_r8(enc, CTL_REG_ESTAT);
|
|
eir_reg = enc_r8(enc, CTL_REG_EIR);
|
|
if (eir_reg & ENC_EIR_TXIF) {
|
|
/* clear TXIF bit in EIR */
|
|
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
|
|
}
|
|
/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
|
|
pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
|
|
if (pkt_cnt > 0) {
|
|
if ((eir_reg & ENC_EIR_PKTIF) == 0) {
|
|
debug("enc_poll: pkt cnt > 0, but pktif not set\n");
|
|
}
|
|
enc_receive(enc);
|
|
/*
|
|
* clear PKTIF bit in EIR, this should not need to be done
|
|
* but it seems like we get problems if we do not
|
|
*/
|
|
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
|
|
}
|
|
if (eir_reg & ENC_EIR_RXERIF) {
|
|
printf("%s: rx error\n", enc->dev->name);
|
|
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
|
|
}
|
|
if (eir_reg & ENC_EIR_TXERIF) {
|
|
printf("%s: tx error\n", enc->dev->name);
|
|
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
|
|
}
|
|
#ifdef CONFIG_USE_IRQ
|
|
/* set global interrupt enable bit in enc28j60 */
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Completely Reset the ENC
|
|
*/
|
|
static void enc_reset(enc_dev_t *enc)
|
|
{
|
|
u8 dout[1];
|
|
|
|
dout[0] = CMD_SRC;
|
|
spi_xfer(enc->slave, 8, dout, NULL,
|
|
SPI_XFER_BEGIN | SPI_XFER_END);
|
|
/* sleep 1 ms. See errata pt. 2 */
|
|
udelay(1000);
|
|
}
|
|
|
|
/*
|
|
* Initialisation data for most of the ENC registers
|
|
*/
|
|
static const u16 enc_initdata[] = {
|
|
/*
|
|
* Setup the buffer space. The reset values are valid for the
|
|
* other pointers.
|
|
*
|
|
* We shall not write to ERXST, see errata pt. 5. Instead we
|
|
* have to make sure that ENC_RX_BUS_START is 0.
|
|
*/
|
|
CTL_REG_ERXSTL, ENC_RX_BUF_START,
|
|
CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
|
|
CTL_REG_ERXNDL, ENC_RX_BUF_END,
|
|
CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
|
|
CTL_REG_ERDPTL, ENC_RX_BUF_START,
|
|
CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
|
|
/*
|
|
* Set the filter to receive only good-CRC, unicast and broadcast
|
|
* frames.
|
|
* Note: some DHCP servers return their answers as broadcasts!
|
|
* So its unwise to remove broadcast from this. This driver
|
|
* might incur receiver overruns with packet loss on a broadcast
|
|
* flooded network.
|
|
*/
|
|
CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
|
|
|
|
/* enable MAC to receive frames */
|
|
CTL_REG_MACON1,
|
|
ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
|
|
|
|
/* configure pad, tx-crc and duplex */
|
|
CTL_REG_MACON3,
|
|
ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
|
|
ENC_MACON3_FRMLNEN,
|
|
|
|
/* Allow infinite deferals if the medium is continously busy */
|
|
CTL_REG_MACON4, ENC_MACON4_DEFER,
|
|
|
|
/* Late collisions occur beyond 63 bytes */
|
|
CTL_REG_MACLCON2, 63,
|
|
|
|
/*
|
|
* Set (low byte) Non-Back-to_Back Inter-Packet Gap.
|
|
* Recommended 0x12
|
|
*/
|
|
CTL_REG_MAIPGL, 0x12,
|
|
|
|
/*
|
|
* Set (high byte) Non-Back-to_Back Inter-Packet Gap.
|
|
* Recommended 0x0c for half-duplex. Nothing for full-duplex
|
|
*/
|
|
CTL_REG_MAIPGH, 0x0C,
|
|
|
|
/* set maximum frame length */
|
|
CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
|
|
CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
|
|
|
|
/*
|
|
* Set MAC back-to-back inter-packet gap.
|
|
* Recommended 0x12 for half duplex
|
|
* and 0x15 for full duplex.
|
|
*/
|
|
CTL_REG_MABBIPG, 0x12,
|
|
|
|
/* end of table */
|
|
0xffff
|
|
};
|
|
|
|
/*
|
|
* Wait for the XTAL oscillator to become ready
|
|
*/
|
|
static int enc_clock_wait(enc_dev_t *enc)
|
|
{
|
|
uint64_t etime;
|
|
|
|
/* one second timeout */
|
|
etime = get_ticks() + get_tbclk();
|
|
|
|
/*
|
|
* Wait for CLKRDY to become set (i.e., check that we can
|
|
* communicate with the ENC)
|
|
*/
|
|
do
|
|
{
|
|
if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
|
|
return 0;
|
|
} while (get_ticks() <= etime);
|
|
|
|
printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Write the MAC address into the ENC
|
|
*/
|
|
static int enc_write_macaddr(enc_dev_t *enc)
|
|
{
|
|
unsigned char *p = enc->dev->enetaddr;
|
|
|
|
enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
|
|
enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
|
|
enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
|
|
enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
|
|
enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
|
|
enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Setup most of the ENC registers
|
|
*/
|
|
static int enc_setup(enc_dev_t *enc)
|
|
{
|
|
u16 phid1 = 0;
|
|
u16 phid2 = 0;
|
|
const u16 *tp;
|
|
|
|
/* reset enc struct values */
|
|
enc->next_pointer = ENC_RX_BUF_START;
|
|
enc->rx_reset_counter = RX_RESET_COUNTER;
|
|
enc->bank = 0xff; /* invalidate current bank in enc28j60 */
|
|
|
|
/* verify PHY identification */
|
|
phid1 = enc_phy_read(enc, PHY_REG_PHID1);
|
|
phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
|
|
if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
|
|
printf("%s: failed to identify PHY. Found %04x:%04x\n",
|
|
enc->dev->name, phid1, phid2);
|
|
return -1;
|
|
}
|
|
|
|
/* now program registers */
|
|
for (tp = enc_initdata; *tp != 0xffff; tp += 2)
|
|
enc_w8_retry(enc, tp[0], tp[1], 10);
|
|
|
|
/*
|
|
* Prevent automatic loopback of data beeing transmitted by setting
|
|
* ENC_PHCON2_HDLDIS
|
|
*/
|
|
enc_phy_write(enc, PHY_REG_PHCON2, (1<<8));
|
|
|
|
/*
|
|
* LEDs configuration
|
|
* LEDA: LACFG = 0100 -> display link status
|
|
* LEDB: LBCFG = 0111 -> display TX & RX activity
|
|
* STRCH = 1 -> LED pulses
|
|
*/
|
|
enc_phy_write(enc, PHY_REG_PHLCON, 0x0472);
|
|
|
|
/* Reset PDPXMD-bit => half duplex */
|
|
enc_phy_write(enc, PHY_REG_PHCON1, 0);
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
/* enable interrupts */
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
|
|
enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check if ENC has been initialized.
|
|
* If not, try to initialize it.
|
|
* Remember initialized state in struct.
|
|
*/
|
|
static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
|
|
{
|
|
if (enc->initstate >= requiredstate)
|
|
return 0;
|
|
|
|
if (enc->initstate < setupdone) {
|
|
/* Initialize the ENC only */
|
|
enc_reset(enc);
|
|
/* if any of functions fails, skip the rest and return an error */
|
|
if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
|
|
return -1;
|
|
}
|
|
enc->initstate = setupdone;
|
|
}
|
|
/* if that's all we need, return here */
|
|
if (enc->initstate >= requiredstate)
|
|
return 0;
|
|
|
|
/* now wait for link ready condition */
|
|
if (enc_phy_link_wait(enc)) {
|
|
return -1;
|
|
}
|
|
enc->initstate = linkready;
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_CMD_MII)
|
|
/*
|
|
* Read a PHY register.
|
|
*
|
|
* This function is registered with miiphy_register().
|
|
*/
|
|
int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
|
|
{
|
|
struct eth_device *dev = eth_get_dev_by_name(devname);
|
|
enc_dev_t *enc;
|
|
|
|
if (!dev || phy_adr != 0)
|
|
return -1;
|
|
|
|
enc = dev->priv;
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, setupdone)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
*value = enc_phy_read(enc, reg);
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write a PHY register.
|
|
*
|
|
* This function is registered with miiphy_register().
|
|
*/
|
|
int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
|
|
{
|
|
struct eth_device *dev = eth_get_dev_by_name(devname);
|
|
enc_dev_t *enc;
|
|
|
|
if (!dev || phy_adr != 0)
|
|
return -1;
|
|
|
|
enc = dev->priv;
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, setupdone)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
enc_phy_write(enc, reg, value);
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Write hardware (MAC) address.
|
|
*
|
|
* This function entered into eth_device structure.
|
|
*/
|
|
static int enc_write_hwaddr(struct eth_device *dev)
|
|
{
|
|
enc_dev_t *enc = dev->priv;
|
|
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, setupdone)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Initialize ENC28J60 for use.
|
|
*
|
|
* This function entered into eth_device structure.
|
|
*/
|
|
static int enc_init(struct eth_device *dev, bd_t *bis)
|
|
{
|
|
enc_dev_t *enc = dev->priv;
|
|
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, linkready)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
/* enable receive */
|
|
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check for received packets.
|
|
*
|
|
* This function entered into eth_device structure.
|
|
*/
|
|
static int enc_recv(struct eth_device *dev)
|
|
{
|
|
enc_dev_t *enc = dev->priv;
|
|
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, linkready)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
/* Check for dead receiver */
|
|
if (enc->rx_reset_counter > 0)
|
|
enc->rx_reset_counter--;
|
|
else
|
|
enc_reset_rx_call(enc);
|
|
enc_poll(enc);
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Send a packet.
|
|
*
|
|
* This function entered into eth_device structure.
|
|
*
|
|
* Should we wait here until we have a Link? Or shall we leave that to
|
|
* protocol retries?
|
|
*/
|
|
static int enc_send(
|
|
struct eth_device *dev,
|
|
void *packet,
|
|
int length)
|
|
{
|
|
enc_dev_t *enc = dev->priv;
|
|
|
|
if (enc_claim_bus(enc))
|
|
return -1;
|
|
if (enc_initcheck(enc, linkready)) {
|
|
enc_release_bus(enc);
|
|
return -1;
|
|
}
|
|
/* setup transmit pointers */
|
|
enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
|
|
enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
|
|
enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
|
|
/* write packet to ENC */
|
|
enc_wbuf(enc, length, (u8 *) packet, 0x00);
|
|
/*
|
|
* Check that the internal transmit logic has not been altered
|
|
* by excessive collisions. Reset transmitter if so.
|
|
* See Errata B4 12 and 14.
|
|
*/
|
|
if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
|
|
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
|
|
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
|
|
}
|
|
enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
|
|
/* start transmitting */
|
|
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
|
|
enc_release_bus(enc);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Finish use of ENC.
|
|
*
|
|
* This function entered into eth_device structure.
|
|
*/
|
|
static void enc_halt(struct eth_device *dev)
|
|
{
|
|
enc_dev_t *enc = dev->priv;
|
|
|
|
if (enc_claim_bus(enc))
|
|
return;
|
|
/* Just disable receiver */
|
|
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
|
|
enc_release_bus(enc);
|
|
}
|
|
|
|
/*
|
|
* This is the only exported function.
|
|
*
|
|
* It may be called several times with different bus:cs combinations.
|
|
*/
|
|
int enc28j60_initialize(unsigned int bus, unsigned int cs,
|
|
unsigned int max_hz, unsigned int mode)
|
|
{
|
|
struct eth_device *dev;
|
|
enc_dev_t *enc;
|
|
|
|
/* try to allocate, check and clear eth_device object */
|
|
dev = malloc(sizeof(*dev));
|
|
if (!dev) {
|
|
return -1;
|
|
}
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
/* try to allocate, check and clear enc_dev_t object */
|
|
enc = malloc(sizeof(*enc));
|
|
if (!enc) {
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
memset(enc, 0, sizeof(*enc));
|
|
|
|
/* try to setup the SPI slave */
|
|
enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
|
|
if (!enc->slave) {
|
|
printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
|
|
free(enc);
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
|
|
enc->dev = dev;
|
|
/* now fill the eth_device object */
|
|
dev->priv = enc;
|
|
dev->init = enc_init;
|
|
dev->halt = enc_halt;
|
|
dev->send = enc_send;
|
|
dev->recv = enc_recv;
|
|
dev->write_hwaddr = enc_write_hwaddr;
|
|
sprintf(dev->name, "enc%i.%i", bus, cs);
|
|
eth_register(dev);
|
|
#if defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
|
|
#endif
|
|
return 0;
|
|
}
|