mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
![Stefan Bosch](/assets/img/avatar_default.png)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - nexell_display.c: Changed to DM, CONFIG_FB_ADDR can not be used anymore because framebuffer is allocated by video_reserve() in video-uclass.c. Therefore code changed appropriately. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). - livetree API (dev_read_...) is used instead of fdt one (fdt...). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
678 lines
15 KiB
C
678 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#include <config.h>
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#include <common.h>
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#include <errno.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/tieoff.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/display.h>
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#include "soc/s5pxx18_soc_mipi.h"
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#include "soc/s5pxx18_soc_disptop.h"
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#include "soc/s5pxx18_soc_disptop_clk.h"
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#define PLLPMS_1000MHZ 0x33E8
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#define BANDCTL_1000MHZ 0xF
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#define PLLPMS_960MHZ 0x2280
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#define BANDCTL_960MHZ 0xF
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#define PLLPMS_900MHZ 0x2258
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#define BANDCTL_900MHZ 0xE
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#define PLLPMS_840MHZ 0x2230
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#define BANDCTL_840MHZ 0xD
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#define PLLPMS_750MHZ 0x43E8
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#define BANDCTL_750MHZ 0xC
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#define PLLPMS_660MHZ 0x21B8
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#define BANDCTL_660MHZ 0xB
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#define PLLPMS_600MHZ 0x2190
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#define BANDCTL_600MHZ 0xA
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#define PLLPMS_540MHZ 0x2168
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#define BANDCTL_540MHZ 0x9
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#define PLLPMS_512MHZ 0x03200
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#define BANDCTL_512MHZ 0x9
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#define PLLPMS_480MHZ 0x2281
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#define BANDCTL_480MHZ 0x8
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#define PLLPMS_420MHZ 0x2231
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#define BANDCTL_420MHZ 0x7
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#define PLLPMS_402MHZ 0x2219
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#define BANDCTL_402MHZ 0x7
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#define PLLPMS_330MHZ 0x21B9
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#define BANDCTL_330MHZ 0x6
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#define PLLPMS_300MHZ 0x2191
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#define BANDCTL_300MHZ 0x5
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#define PLLPMS_210MHZ 0x2232
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#define BANDCTL_210MHZ 0x4
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#define PLLPMS_180MHZ 0x21E2
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#define BANDCTL_180MHZ 0x3
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#define PLLPMS_150MHZ 0x2192
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#define BANDCTL_150MHZ 0x2
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#define PLLPMS_100MHZ 0x3323
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#define BANDCTL_100MHZ 0x1
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#define PLLPMS_80MHZ 0x3283
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#define BANDCTL_80MHZ 0x0
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#define MIPI_INDEX 0
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#define MIPI_EXC_PRE_VALUE 1
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#define MIPI_DSI_IRQ_MASK 29
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#define __io_address(a) (void *)(uintptr_t)(a)
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struct mipi_xfer_msg {
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u8 id, data[2];
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u16 flags;
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const u8 *tx_buf;
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u16 tx_len;
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u8 *rx_buf;
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u16 rx_len;
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};
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static void mipi_reset(void)
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{
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/* tieoff */
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nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
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nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
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/* reset */
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nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_MIPI_CSI, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_NEGATE);
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nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_NEGATE);
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nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_NEGATE);
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nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_NEGATE);
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}
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static void mipi_init(void)
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{
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int clkid = DP_CLOCK_MIPI;
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void *base;
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/*
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* neet to reset before open
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*/
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mipi_reset();
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base = __io_address(nx_disp_top_clkgen_get_physical_address(clkid));
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nx_disp_top_clkgen_set_base_address(clkid, base);
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nx_disp_top_clkgen_set_clock_pclk_mode(clkid, nx_pclkmode_always);
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base = __io_address(nx_mipi_get_physical_address(0));
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nx_mipi_set_base_address(0, base);
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}
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static int mipi_get_phy_pll(int bitrate, unsigned int *pllpms,
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unsigned int *bandctl)
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{
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unsigned int pms, ctl;
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switch (bitrate) {
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case 1000:
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pms = PLLPMS_1000MHZ;
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ctl = BANDCTL_1000MHZ;
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break;
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case 960:
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pms = PLLPMS_960MHZ;
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ctl = BANDCTL_960MHZ;
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break;
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case 900:
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pms = PLLPMS_900MHZ;
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ctl = BANDCTL_900MHZ;
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break;
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case 840:
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pms = PLLPMS_840MHZ;
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ctl = BANDCTL_840MHZ;
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break;
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case 750:
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pms = PLLPMS_750MHZ;
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ctl = BANDCTL_750MHZ;
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break;
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case 660:
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pms = PLLPMS_660MHZ;
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ctl = BANDCTL_660MHZ;
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break;
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case 600:
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pms = PLLPMS_600MHZ;
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ctl = BANDCTL_600MHZ;
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break;
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case 540:
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pms = PLLPMS_540MHZ;
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ctl = BANDCTL_540MHZ;
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break;
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case 512:
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pms = PLLPMS_512MHZ;
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ctl = BANDCTL_512MHZ;
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break;
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case 480:
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pms = PLLPMS_480MHZ;
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ctl = BANDCTL_480MHZ;
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break;
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case 420:
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pms = PLLPMS_420MHZ;
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ctl = BANDCTL_420MHZ;
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break;
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case 402:
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pms = PLLPMS_402MHZ;
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ctl = BANDCTL_402MHZ;
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break;
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case 330:
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pms = PLLPMS_330MHZ;
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ctl = BANDCTL_330MHZ;
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break;
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case 300:
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pms = PLLPMS_300MHZ;
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ctl = BANDCTL_300MHZ;
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break;
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case 210:
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pms = PLLPMS_210MHZ;
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ctl = BANDCTL_210MHZ;
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break;
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case 180:
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pms = PLLPMS_180MHZ;
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ctl = BANDCTL_180MHZ;
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break;
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case 150:
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pms = PLLPMS_150MHZ;
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ctl = BANDCTL_150MHZ;
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break;
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case 100:
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pms = PLLPMS_100MHZ;
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ctl = BANDCTL_100MHZ;
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break;
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case 80:
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pms = PLLPMS_80MHZ;
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ctl = BANDCTL_80MHZ;
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break;
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default:
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return -EINVAL;
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}
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*pllpms = pms;
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*bandctl = ctl;
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return 0;
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}
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static int mipi_prepare(int module, int input,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_mipi_dev *mipi)
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{
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int index = MIPI_INDEX;
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u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
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int lpm = mipi->lpm_trans;
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int ret = 0;
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ret = mipi_get_phy_pll(mipi->hs_bitrate,
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&mipi->hs_pllpms, &mipi->hs_bandctl);
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if (ret < 0)
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return ret;
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ret = mipi_get_phy_pll(mipi->lp_bitrate,
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&mipi->lp_pllpms, &mipi->lp_bandctl);
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if (ret < 0)
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return ret;
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debug("%s: mipi lp:%dmhz:0x%x:0x%x, hs:%dmhz:0x%x:0x%x, %s trans\n",
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__func__, mipi->lp_bitrate, mipi->lp_pllpms, mipi->lp_bandctl,
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mipi->hs_bitrate, mipi->hs_pllpms, mipi->hs_bandctl,
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lpm ? "low" : "high");
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if (lpm)
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nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
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mipi->lp_pllpms, mipi->lp_bandctl, 0, 0);
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else
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nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
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mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
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#ifdef CONFIG_ARCH_S5P4418
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/*
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* disable the escape clock generating prescaler
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* before soft reset.
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*/
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nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 0, 10);
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mdelay(1);
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#endif
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nx_mipi_dsi_software_reset(index);
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nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 1, esc_pre_value);
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nx_mipi_dsi_set_phy(index, 0, 1, 1, 0, 0, 0, 0, 0);
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if (lpm)
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nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_lp,
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nx_mipi_dsi_lpmode_lp);
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else
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nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_hs,
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nx_mipi_dsi_lpmode_hs);
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mdelay(20);
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return 0;
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}
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static int mipi_enable(int module, int input,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_mipi_dev *mipi)
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{
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struct mipi_dsi_device *dsi = &mipi->dsi;
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int clkid = DP_CLOCK_MIPI;
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int index = MIPI_INDEX;
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int width = sync->h_active_len;
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int height = sync->v_active_len;
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int HFP = sync->h_front_porch;
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int HBP = sync->h_back_porch;
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int HS = sync->h_sync_width;
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int VFP = sync->v_front_porch;
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int VBP = sync->v_back_porch;
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int VS = sync->v_sync_width;
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int en_prescaler = 1;
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u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
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int txhsclock = 1;
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int lpm = mipi->lpm_trans;
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bool command_mode = mipi->command_mode;
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enum nx_mipi_dsi_format dsi_format;
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int data_len = dsi->lanes - 1;
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bool burst = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? true : false;
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bool eot_enable = dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ?
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false : true;
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/*
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* disable the escape clock generating prescaler
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* before soft reset.
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*/
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#ifdef CONFIG_ARCH_S5P4418
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en_prescaler = 0;
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#endif
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debug("%s: mode:%s, lanes.%d\n", __func__,
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command_mode ? "command" : "video", data_len + 1);
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if (lpm)
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nx_mipi_dsi_set_escape_lp(index,
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nx_mipi_dsi_lpmode_hs,
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nx_mipi_dsi_lpmode_hs);
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nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
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mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
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mdelay(1);
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nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, en_prescaler, 10);
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mdelay(1);
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nx_mipi_dsi_software_reset(index);
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nx_mipi_dsi_set_clock(index, txhsclock, 0, 1,
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1, 1, 0, 0, 0, 1, esc_pre_value);
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switch (data_len) {
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case 0: /* 1 lane */
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nx_mipi_dsi_set_phy(index, data_len, 1, 1, 0, 0, 0, 0, 0);
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break;
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case 1: /* 2 lane */
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nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 0, 0, 0, 0);
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break;
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case 2: /* 3 lane */
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nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 0, 0, 0);
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break;
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case 3: /* 3 lane */
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nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 1, 0, 0);
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break;
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default:
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printf("%s: not support data lanes %d\n",
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__func__, data_len + 1);
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return -EINVAL;
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}
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switch (dsi->format) {
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case MIPI_DSI_FMT_RGB565:
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dsi_format = nx_mipi_dsi_format_rgb565;
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break;
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case MIPI_DSI_FMT_RGB666:
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dsi_format = nx_mipi_dsi_format_rgb666;
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break;
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case MIPI_DSI_FMT_RGB666_PACKED:
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dsi_format = nx_mipi_dsi_format_rgb666_packed;
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break;
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case MIPI_DSI_FMT_RGB888:
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dsi_format = nx_mipi_dsi_format_rgb888;
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break;
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default:
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printf("%s: not support format %d\n", __func__, dsi->format);
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return -EINVAL;
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}
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nx_mipi_dsi_set_config_video_mode(index, 1, 0, burst,
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nx_mipi_dsi_syncmode_event,
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eot_enable, 1, 1, 1, 1, 0, dsi_format,
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HFP, HBP, HS, VFP, VBP, VS, 0);
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nx_mipi_dsi_set_size(index, width, height);
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/* set mux */
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nx_disp_top_set_mipimux(1, module);
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/* 0 is spdif, 1 is mipi vclk */
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nx_disp_top_clkgen_set_clock_source(clkid, 1, ctrl->clk_src_lv0);
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nx_disp_top_clkgen_set_clock_divisor(clkid, 1,
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ctrl->clk_div_lv1 *
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ctrl->clk_div_lv0);
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/* SPDIF and MIPI */
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nx_disp_top_clkgen_set_clock_divisor_enable(clkid, 1);
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/* START: CLKGEN, MIPI is started in setup function */
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nx_disp_top_clkgen_set_clock_divisor_enable(clkid, true);
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nx_mipi_dsi_set_enable(index, true);
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return 0;
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}
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static int nx_mipi_transfer_tx(struct mipi_dsi_device *dsi,
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struct mipi_xfer_msg *xfer)
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{
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const u8 *txb;
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int size, index = 0;
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u32 data;
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if (xfer->tx_len > DSI_TX_FIFO_SIZE)
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printf("warn: tx %d size over fifo %d\n",
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(int)xfer->tx_len, DSI_TX_FIFO_SIZE);
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/* write payload */
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size = xfer->tx_len;
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txb = xfer->tx_buf;
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while (size >= 4) {
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data = (txb[3] << 24) | (txb[2] << 16) |
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(txb[1] << 8) | (txb[0]);
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nx_mipi_dsi_write_payload(index, data);
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txb += 4, size -= 4;
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data = 0;
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}
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switch (size) {
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case 3:
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data |= txb[2] << 16;
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case 2:
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data |= txb[1] << 8;
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case 1:
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data |= txb[0];
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nx_mipi_dsi_write_payload(index, data);
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break;
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case 0:
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break; /* no payload */
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}
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/* write packet hdr */
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data = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->id;
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nx_mipi_dsi_write_pkheader(index, data);
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return 0;
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}
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static int nx_mipi_transfer_done(struct mipi_dsi_device *dsi)
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{
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int index = 0, count = 100;
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u32 value;
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do {
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mdelay(1);
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value = nx_mipi_dsi_read_fifo_status(index);
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if (((1 << 22) & value))
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break;
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} while (count-- > 0);
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if (count < 0)
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return -EINVAL;
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return 0;
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}
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static int nx_mipi_transfer_rx(struct mipi_dsi_device *dsi,
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struct mipi_xfer_msg *xfer)
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{
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u8 *rxb = xfer->rx_buf;
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int index = 0, rx_len = 0;
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u32 data, count = 0;
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u16 size;
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int err = -EINVAL;
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nx_mipi_dsi_clear_interrupt_pending(index, 18);
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while (1) {
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/* Completes receiving data. */
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if (nx_mipi_dsi_get_interrupt_pending(index, 18))
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break;
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mdelay(1);
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if (count > 500) {
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printf("%s: error recevice data\n", __func__);
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err = -EINVAL;
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goto clear_fifo;
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} else {
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count++;
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}
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}
|
|
|
|
data = nx_mipi_dsi_read_fifo(index);
|
|
|
|
switch (data & 0x3f) {
|
|
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
|
|
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
|
|
if (xfer->rx_len >= 2) {
|
|
rxb[1] = data >> 16;
|
|
rx_len++;
|
|
}
|
|
|
|
/* Fall through */
|
|
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
|
|
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
|
|
rxb[0] = data >> 8;
|
|
rx_len++;
|
|
xfer->rx_len = rx_len;
|
|
err = rx_len;
|
|
goto clear_fifo;
|
|
|
|
case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
|
|
printf("DSI Error Report: 0x%04x\n", (data >> 8) & 0xffff);
|
|
err = rx_len;
|
|
goto clear_fifo;
|
|
}
|
|
|
|
size = (data >> 8) & 0xffff;
|
|
|
|
if (size > xfer->rx_len)
|
|
size = xfer->rx_len;
|
|
else if (size < xfer->rx_len)
|
|
xfer->rx_len = size;
|
|
|
|
size = xfer->rx_len - rx_len;
|
|
rx_len += size;
|
|
|
|
/* Receive payload */
|
|
while (size >= 4) {
|
|
data = nx_mipi_dsi_read_fifo(index);
|
|
rxb[0] = (data >> 0) & 0xff;
|
|
rxb[1] = (data >> 8) & 0xff;
|
|
rxb[2] = (data >> 16) & 0xff;
|
|
rxb[3] = (data >> 24) & 0xff;
|
|
rxb += 4, size -= 4;
|
|
}
|
|
|
|
if (size) {
|
|
data = nx_mipi_dsi_read_fifo(index);
|
|
switch (size) {
|
|
case 3:
|
|
rxb[2] = (data >> 16) & 0xff;
|
|
case 2:
|
|
rxb[1] = (data >> 8) & 0xff;
|
|
case 1:
|
|
rxb[0] = data & 0xff;
|
|
}
|
|
}
|
|
|
|
if (rx_len == xfer->rx_len)
|
|
err = rx_len;
|
|
|
|
clear_fifo:
|
|
size = DSI_RX_FIFO_SIZE / 4;
|
|
do {
|
|
data = nx_mipi_dsi_read_fifo(index);
|
|
if (data == DSI_RX_FIFO_EMPTY)
|
|
break;
|
|
} while (--size);
|
|
|
|
return err;
|
|
}
|
|
|
|
#define IS_SHORT(t) (9 > ((t) & 0x0f))
|
|
|
|
static int nx_mipi_transfer(struct mipi_dsi_device *dsi,
|
|
const struct mipi_dsi_msg *msg)
|
|
{
|
|
struct mipi_xfer_msg xfer;
|
|
int err;
|
|
|
|
if (!msg->tx_len)
|
|
return -EINVAL;
|
|
|
|
/* set id */
|
|
xfer.id = msg->type | (msg->channel << 6);
|
|
|
|
/* short type msg */
|
|
if (IS_SHORT(msg->type)) {
|
|
const char *txb = msg->tx_buf;
|
|
|
|
if (msg->tx_len > 2)
|
|
return -EINVAL;
|
|
|
|
xfer.tx_len = 0; /* no payload */
|
|
xfer.data[0] = txb[0];
|
|
xfer.data[1] = (msg->tx_len == 2) ? txb[1] : 0;
|
|
xfer.tx_buf = NULL;
|
|
} else {
|
|
xfer.tx_len = msg->tx_len;
|
|
xfer.data[0] = msg->tx_len & 0xff;
|
|
xfer.data[1] = msg->tx_len >> 8;
|
|
xfer.tx_buf = msg->tx_buf;
|
|
}
|
|
|
|
xfer.rx_len = msg->rx_len;
|
|
xfer.rx_buf = msg->rx_buf;
|
|
xfer.flags = msg->flags;
|
|
|
|
err = nx_mipi_transfer_tx(dsi, &xfer);
|
|
|
|
if (xfer.rx_len)
|
|
err = nx_mipi_transfer_rx(dsi, &xfer);
|
|
|
|
nx_mipi_transfer_done(dsi);
|
|
|
|
return err;
|
|
}
|
|
|
|
static ssize_t nx_mipi_write_buffer(struct mipi_dsi_device *dsi,
|
|
const void *data, size_t len)
|
|
{
|
|
struct mipi_dsi_msg msg = {
|
|
.channel = dsi->channel,
|
|
.tx_buf = data,
|
|
.tx_len = len
|
|
};
|
|
|
|
switch (len) {
|
|
case 0:
|
|
return -EINVAL;
|
|
case 1:
|
|
msg.type = MIPI_DSI_DCS_SHORT_WRITE;
|
|
break;
|
|
case 2:
|
|
msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
|
|
break;
|
|
default:
|
|
msg.type = MIPI_DSI_DCS_LONG_WRITE;
|
|
break;
|
|
}
|
|
|
|
if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
|
|
msg.flags |= MIPI_DSI_MSG_USE_LPM;
|
|
|
|
return nx_mipi_transfer(dsi, &msg);
|
|
}
|
|
|
|
__weak int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* disply
|
|
* MIPI DSI Setting
|
|
* (1) Initiallize MIPI(DSIM,DPHY,PLL)
|
|
* (2) Initiallize LCD
|
|
* (3) ReInitiallize MIPI(DSIM only)
|
|
* (4) Turn on display(MLC,DPC,...)
|
|
*/
|
|
void nx_mipi_display(int module,
|
|
struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
|
|
struct dp_plane_top *top, struct dp_plane_info *planes,
|
|
struct dp_mipi_dev *dev)
|
|
{
|
|
struct dp_plane_info *plane = planes;
|
|
struct mipi_dsi_device *dsi = &dev->dsi;
|
|
int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1;
|
|
int count = top->plane_num;
|
|
int i = 0, ret;
|
|
|
|
printf("MIPI: dp.%d\n", module);
|
|
|
|
/* map mipi-dsi write callback func */
|
|
dsi->write_buffer = nx_mipi_write_buffer;
|
|
|
|
ret = nx_mipi_dsi_lcd_bind(dsi);
|
|
if (ret) {
|
|
printf("Error: bind mipi-dsi lcd driver !\n");
|
|
return;
|
|
}
|
|
|
|
dp_control_init(module);
|
|
dp_plane_init(module);
|
|
|
|
mipi_init();
|
|
|
|
/* set plane */
|
|
dp_plane_screen_setup(module, top);
|
|
|
|
for (i = 0; count > i; i++, plane++) {
|
|
if (!plane->enable)
|
|
continue;
|
|
dp_plane_layer_setup(module, plane);
|
|
dp_plane_layer_enable(module, plane, 1);
|
|
}
|
|
dp_plane_screen_enable(module, 1);
|
|
|
|
/* set mipi */
|
|
mipi_prepare(module, input, sync, ctrl, dev);
|
|
|
|
if (dsi->ops && dsi->ops->prepare)
|
|
dsi->ops->prepare(dsi);
|
|
|
|
if (dsi->ops && dsi->ops->enable)
|
|
dsi->ops->enable(dsi);
|
|
|
|
mipi_enable(module, input, sync, ctrl, dev);
|
|
|
|
/* set dp control */
|
|
dp_control_setup(module, sync, ctrl);
|
|
dp_control_enable(module, 1);
|
|
}
|