mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
![Stefan Bosch](/assets/img/avatar_default.png)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - nexell_display.c: Changed to DM, CONFIG_FB_ADDR can not be used anymore because framebuffer is allocated by video_reserve() in video-uclass.c. Therefore code changed appropriately. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). - livetree API (dev_read_...) is used instead of fdt one (fdt...). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
342 lines
10 KiB
C
342 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#include <config.h>
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/display.h>
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#include "soc/s5pxx18_soc_disptop.h"
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#include "soc/s5pxx18_soc_dpc.h"
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#include "soc/s5pxx18_soc_mlc.h"
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#define MLC_LAYER_RGB_0 0 /* number of RGB layer 0 */
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#define MLC_LAYER_RGB_1 1 /* number of RGB layer 1 */
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#define MLC_LAYER_VIDEO 3 /* number of Video layer: 3 = VIDEO */
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#define __io_address(a) (void *)(uintptr_t)(a)
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void dp_control_init(int module)
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{
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void *base;
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/* top */
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base = __io_address(nx_disp_top_get_physical_address());
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nx_disp_top_set_base_address(base);
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/* control */
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base = __io_address(nx_dpc_get_physical_address(module));
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nx_dpc_set_base_address(module, base);
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/* top controller */
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nx_rstcon_setrst(RESET_ID_DISP_TOP, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_DISP_TOP, RSTCON_NEGATE);
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/* display controller */
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nx_rstcon_setrst(RESET_ID_DISPLAY, RSTCON_ASSERT);
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nx_rstcon_setrst(RESET_ID_DISPLAY, RSTCON_NEGATE);
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nx_dpc_set_clock_pclk_mode(module, nx_pclkmode_always);
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}
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int dp_control_setup(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl)
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{
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unsigned int out_format;
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unsigned int delay_mask;
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int rgb_pvd = 0, hsync_cp1 = 7, vsync_fram = 7, de_cp2 = 7;
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int v_vso = 1, v_veo = 1, e_vso = 1, e_veo = 1;
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int interlace = 0;
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int invert_field;
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int swap_rb;
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unsigned int yc_order;
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int vck_select;
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int vclk_invert;
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int emb_sync;
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enum nx_dpc_dither r_dither, g_dither, b_dither;
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int rgb_mode = 0;
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if (NULL == sync || NULL == ctrl) {
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debug("error, dp.%d not set sync or pad clock info !!!\n",
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module);
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return -EINVAL;
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}
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out_format = ctrl->out_format;
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delay_mask = ctrl->delay_mask;
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interlace = sync->interlace;
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invert_field = ctrl->invert_field;
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swap_rb = ctrl->swap_RB;
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yc_order = ctrl->yc_order;
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vck_select = ctrl->vck_select;
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vclk_invert = ctrl->clk_inv_lv0 | ctrl->clk_inv_lv1;
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emb_sync = (out_format == DPC_FORMAT_CCIR656 ? 1 : 0);
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/* set delay mask */
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if (delay_mask & DP_SYNC_DELAY_RGB_PVD)
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rgb_pvd = ctrl->d_rgb_pvd;
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if (delay_mask & DP_SYNC_DELAY_HSYNC_CP1)
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hsync_cp1 = ctrl->d_hsync_cp1;
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if (delay_mask & DP_SYNC_DELAY_VSYNC_FRAM)
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vsync_fram = ctrl->d_vsync_fram;
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if (delay_mask & DP_SYNC_DELAY_DE_CP)
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de_cp2 = ctrl->d_de_cp2;
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if (ctrl->vs_start_offset != 0 ||
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ctrl->vs_end_offset != 0 ||
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ctrl->ev_start_offset != 0 || ctrl->ev_end_offset != 0) {
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v_vso = ctrl->vs_start_offset;
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v_veo = ctrl->vs_end_offset;
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e_vso = ctrl->ev_start_offset;
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e_veo = ctrl->ev_end_offset;
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}
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if (nx_dpc_format_rgb555 == out_format ||
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nx_dpc_format_mrgb555a == out_format ||
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nx_dpc_format_mrgb555b == out_format) {
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r_dither = nx_dpc_dither_5bit;
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g_dither = nx_dpc_dither_5bit;
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b_dither = nx_dpc_dither_5bit;
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rgb_mode = 1;
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} else if (nx_dpc_format_rgb565 == out_format ||
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nx_dpc_format_mrgb565 == out_format) {
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r_dither = nx_dpc_dither_5bit;
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b_dither = nx_dpc_dither_5bit;
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g_dither = nx_dpc_dither_6bit, rgb_mode = 1;
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} else if ((nx_dpc_format_rgb666 == out_format) ||
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(nx_dpc_format_mrgb666 == out_format)) {
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r_dither = nx_dpc_dither_6bit;
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g_dither = nx_dpc_dither_6bit;
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b_dither = nx_dpc_dither_6bit;
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rgb_mode = 1;
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} else {
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r_dither = nx_dpc_dither_bypass;
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g_dither = nx_dpc_dither_bypass;
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b_dither = nx_dpc_dither_bypass;
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rgb_mode = 1;
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}
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/* CLKGEN0/1 */
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nx_dpc_set_clock_source(module, 0, ctrl->clk_src_lv0 == 3 ?
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6 : ctrl->clk_src_lv0);
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nx_dpc_set_clock_divisor(module, 0, ctrl->clk_div_lv0);
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nx_dpc_set_clock_source(module, 1, ctrl->clk_src_lv1);
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nx_dpc_set_clock_divisor(module, 1, ctrl->clk_div_lv1);
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nx_dpc_set_clock_out_delay(module, 0, ctrl->clk_delay_lv0);
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nx_dpc_set_clock_out_delay(module, 1, ctrl->clk_delay_lv1);
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/* LCD out */
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nx_dpc_set_mode(module, out_format, interlace, invert_field,
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rgb_mode, swap_rb, yc_order, emb_sync, emb_sync,
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vck_select, vclk_invert, 0);
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nx_dpc_set_hsync(module, sync->h_active_len, sync->h_sync_width,
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sync->h_front_porch, sync->h_back_porch,
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sync->h_sync_invert);
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nx_dpc_set_vsync(module, sync->v_active_len, sync->v_sync_width,
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sync->v_front_porch, sync->v_back_porch,
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sync->v_sync_invert, sync->v_active_len,
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sync->v_sync_width, sync->v_front_porch,
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sync->v_back_porch);
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nx_dpc_set_vsync_offset(module, v_vso, v_veo, e_vso, e_veo);
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nx_dpc_set_delay(module, rgb_pvd, hsync_cp1, vsync_fram, de_cp2);
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nx_dpc_set_dither(module, r_dither, g_dither, b_dither);
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if (IS_ENABLED(CONFIG_MACH_S5P6818)) {
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/* Set TFT_CLKCTRL (offset : 1030h)
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* Field name : DPC0_CLKCTRL, DPC1_CLKCRL
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* Default value : clk_inv_lv0/1 = 0 : PADCLK_InvCLK
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* Invert case : clk_inv_lv0/1 = 1 : PADCLK_CLK
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*/
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if (module == 0 && ctrl->clk_inv_lv0)
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nx_disp_top_set_padclock(padmux_primary_mlc,
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padclk_clk);
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if (module == 1 && ctrl->clk_inv_lv1)
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nx_disp_top_set_padclock(padmux_secondary_mlc,
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padclk_clk);
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}
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debug("%s: dp.%d x:%4d, hf:%3d, hb:%3d, hs:%3d, hi=%d\n",
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__func__, module, sync->h_active_len, sync->h_front_porch,
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sync->h_back_porch, sync->h_sync_width, sync->h_sync_invert);
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debug("%s: dp.%d y:%4d, vf:%3d, vb:%3d, vs:%3d, vi=%d\n",
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__func__, module, sync->v_active_len, sync->v_front_porch,
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sync->v_back_porch, sync->v_sync_width, sync->h_sync_invert);
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debug("%s: dp.%d ck.0:%d:%d:%d, ck.1:%d:%d:%d\n",
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__func__, module,
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ctrl->clk_src_lv0, ctrl->clk_div_lv0, ctrl->clk_inv_lv0,
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ctrl->clk_src_lv1, ctrl->clk_div_lv1, ctrl->clk_inv_lv1);
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debug("%s: dp.%d vs:%d, ve:%d, es:%d, ee:%d\n",
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__func__, module, v_vso, v_veo, e_vso, e_veo);
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debug("%s: dp.%d delay RGB:%d, hs:%d, vs:%d, de:%d, fmt:0x%x\n",
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__func__, module, rgb_pvd, hsync_cp1, vsync_fram, de_cp2,
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out_format);
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return 0;
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}
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void dp_control_enable(int module, int on)
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{
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debug("%s: dp.%d top %s\n", __func__, module, on ? "ON" : "OFF");
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nx_dpc_set_dpc_enable(module, on);
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nx_dpc_set_clock_divisor_enable(module, on);
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}
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void dp_plane_init(int module)
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{
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void *base = __io_address(nx_mlc_get_physical_address(module));
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nx_mlc_set_base_address(module, base);
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nx_mlc_set_clock_pclk_mode(module, nx_pclkmode_always);
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nx_mlc_set_clock_bclk_mode(module, nx_bclkmode_always);
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}
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int dp_plane_screen_setup(int module, struct dp_plane_top *top)
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{
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int width = top->screen_width;
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int height = top->screen_height;
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int interlace = top->interlace;
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int video_prior = top->video_prior;
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unsigned int bg_color = top->back_color;
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/* MLC TOP layer */
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nx_mlc_set_screen_size(module, width, height);
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nx_mlc_set_layer_priority(module, video_prior);
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nx_mlc_set_background(module, bg_color);
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nx_mlc_set_field_enable(module, interlace);
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nx_mlc_set_rgblayer_gama_table_power_mode(module, 0, 0, 0);
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nx_mlc_set_rgblayer_gama_table_sleep_mode(module, 1, 1, 1);
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nx_mlc_set_rgblayer_gamma_enable(module, 0);
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nx_mlc_set_dither_enable_when_using_gamma(module, 0);
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nx_mlc_set_gamma_priority(module, 0);
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nx_mlc_set_top_power_mode(module, 1);
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nx_mlc_set_top_sleep_mode(module, 0);
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debug("%s: dp.%d screen %dx%d, %s, priority:%d, bg:0x%x\n",
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__func__, module, width, height,
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interlace ? "Interlace" : "Progressive",
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video_prior, bg_color);
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return 0;
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}
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void dp_plane_screen_enable(int module, int on)
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{
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/* enable top screen */
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nx_mlc_set_mlc_enable(module, on);
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nx_mlc_set_top_dirty_flag(module);
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debug("%s: dp.%d top %s\n", __func__, module, on ? "ON" : "OFF");
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}
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int dp_plane_layer_setup(int module, struct dp_plane_info *plane)
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{
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int sx = plane->left;
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int sy = plane->top;
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int ex = sx + plane->width - 1;
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int ey = sy + plane->height - 1;
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int pixel_byte = plane->pixel_byte;
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int mem_lock_size = 16; /* fix mem lock size */
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int layer = plane->layer;
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unsigned int format = plane->format;
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if (!plane->enable)
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return -EINVAL;
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/* MLC layer */
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nx_mlc_set_lock_size(module, layer, mem_lock_size);
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nx_mlc_set_alpha_blending(module, layer, 0, 15);
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nx_mlc_set_transparency(module, layer, 0, 0);
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nx_mlc_set_color_inversion(module, layer, 0, 0);
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nx_mlc_set_rgblayer_invalid_position(module, layer, 0, 0, 0, 0, 0, 0);
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nx_mlc_set_rgblayer_invalid_position(module, layer, 1, 0, 0, 0, 0, 0);
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nx_mlc_set_format_rgb(module, layer, format);
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nx_mlc_set_position(module, layer, sx, sy, ex, ey);
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nx_mlc_set_rgblayer_stride(module, layer, pixel_byte,
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plane->width * pixel_byte);
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nx_mlc_set_rgblayer_address(module, layer, plane->fb_base);
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debug("%s: dp.%d.%d %d * %d, %dbpp, fmt:0x%x\n",
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__func__, module, layer, plane->width, plane->height,
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pixel_byte * 8, format);
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debug("%s: b:0x%x, l:%d, t:%d, r:%d, b:%d, hs:%d, vs:%d\n",
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__func__, plane->fb_base, sx, sy, ex, ey,
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plane->width * pixel_byte, pixel_byte);
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return 0;
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}
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int dp_plane_set_enable(int module, int layer, int on)
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{
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int hl, hc;
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int vl, vc;
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debug("%s: dp.%d.%d %s:%s\n",
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__func__, module, layer,
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layer == MLC_LAYER_VIDEO ? "Video" : "RGB",
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on ? "ON" : "OFF");
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if (layer != MLC_LAYER_VIDEO) {
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nx_mlc_set_layer_enable(module, layer, on);
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nx_mlc_set_dirty_flag(module, layer);
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return 0;
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}
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/* video layer */
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if (on) {
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nx_mlc_set_video_layer_line_buffer_power_mode(module, 1);
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nx_mlc_set_video_layer_line_buffer_sleep_mode(module, 0);
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nx_mlc_set_layer_enable(module, layer, 1);
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nx_mlc_set_dirty_flag(module, layer);
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} else {
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nx_mlc_set_layer_enable(module, layer, 0);
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nx_mlc_set_dirty_flag(module, layer);
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nx_mlc_get_video_layer_scale_filter(module,
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&hl, &hc, &vl, &vc);
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if (hl || hc || vl || vc)
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nx_mlc_set_video_layer_scale_filter(module, 0, 0, 0, 0);
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nx_mlc_set_video_layer_line_buffer_power_mode(module, 0);
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nx_mlc_set_video_layer_line_buffer_sleep_mode(module, 1);
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nx_mlc_set_dirty_flag(module, layer);
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}
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return 0;
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}
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void dp_plane_layer_enable(int module,
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struct dp_plane_info *plane, int on)
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{
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dp_plane_set_enable(module, plane->layer, on);
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}
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int dp_plane_set_address(int module, int layer, unsigned int address)
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{
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nx_mlc_set_rgblayer_address(module, layer, address);
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nx_mlc_set_dirty_flag(module, layer);
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return 0;
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}
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int dp_plane_wait_vsync(int module, int layer, int fps)
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{
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int cnt = 0;
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if (fps == 0)
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return (int)nx_mlc_get_dirty_flag(module, layer);
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while (fps > cnt++) {
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while (nx_mlc_get_dirty_flag(module, layer))
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;
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nx_mlc_set_dirty_flag(module, layer);
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}
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return 0;
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}
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