mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-16 23:18:51 +09:00
209 lines
5.8 KiB
C
209 lines
5.8 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* (C) Copyright 2001
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* Torsten Stevens, FHG IMS, stevens@ims.fhg.de
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* Bruno Achauer, Exet AG, bruno@exet-ag.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Derived from ../tqm8xx/tqm8xx.c
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
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0x1ff77c47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7ffffc07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test TQ ID string (TQM8xx...)
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* If present, check for "L" type (no second DRAM bank),
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* otherwise "L" type is assumed as default.
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*
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* Return 1 for "L" type, 0 else.
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*/
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int checkboard (void)
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{
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printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0;
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int i;
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/*
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* Configure UPMA for SDRAM
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*/
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
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/* burst length=4, burst type=sequential, CAS latency=2 */
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 3 to the SDRAM bank at preliminary address.
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*/
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memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
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/* initialize memory address register */
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
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/* mode initialization (offset 5) */
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udelay (200); /* 0x80006105 */
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memctl->memc_mcr =
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MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
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/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
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udelay (1); /* 0x80006130 */
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memctl->memc_mcr =
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MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
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udelay (1); /* 0x80006130 */
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memctl->memc_mcr =
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MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
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udelay (1); /* 0x80006106 */
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memctl->memc_mcr =
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MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
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memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
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udelay (200);
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/* Need at least 10 DRAM accesses to stabilize */
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for (i = 0; i < 10; ++i) {
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volatile unsigned long *addr =
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(volatile unsigned long *) SDRAM_BASE3_PRELIM;
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unsigned long val;
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val = *(addr + i);
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*(addr + i) = val;
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}
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/*
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* Check Bank 0 Memory Size for re-configuration
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*/
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size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
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(long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
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/*
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* Final mapping:
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*/
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memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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udelay (1000);
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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