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https://github.com/brain-hackers/u-boot-brain
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712cf7ab0b
It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust; /* Range: 0-8 */
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u32 cpo; /* Range: 2-31 */
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u32 write_data_delay; /* Range: 0-6 */
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u32 force_2T;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters dimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{1, 549, 5, 31, 3, 0},
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{1, 850, 5, 31, 5, 0},
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{2, 549, 5, 31, 3, 0},
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{2, 850, 5, 31, 5, 0},
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{}
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};
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void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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unsigned long ddr_freq;
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unsigned int i;
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if (ctrl_num) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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/* set odt_rd_cfg and odt_wr_cfg. */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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pbsp = dimm0;
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2T;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s!\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2T;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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popts->half_strength_driver_enable = 1;
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/* Per AN4039, enable ZQ calibration. */
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popts->zq_en = 1;
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/*
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* For wake-up on ARP, we need auto self refresh enabled
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*/
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popts->auto_self_refresh_en = 1;
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popts->sr_it = 0xb;
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}
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