mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
123 lines
2.6 KiB
C
123 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <asm/fsl_serdes.h>
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#include <linux/errno.h>
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#include "kmp204x.h"
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#define PROM_SEL_L 11
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/* control the PROM_SEL_L signal*/
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static void toggle_fpga_eeprom_bus(bool cpu_own)
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{
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qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
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}
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#define CONF_SEL_L 10
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#define FPGA_PROG_L 19
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#define FPGA_DONE 18
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#define FPGA_INIT_L 17
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int trigger_fpga_config(void)
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{
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int ret = 0, init_l;
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/* approx 10ms */
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u32 timeout = 10000;
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/* make sure the FPGA_can access the EEPROM */
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toggle_fpga_eeprom_bus(false);
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/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
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qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
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/* trigger the config start */
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qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
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/* small delay for INIT_L line */
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udelay(10);
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/* wait for FPGA_INIT to be asserted */
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do {
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init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
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if (timeout-- == 0) {
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printf("FPGA_INIT timeout\n");
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ret = -EFAULT;
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break;
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}
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udelay(10);
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} while (init_l);
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/* deassert FPGA_PROG, config should start */
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qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
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return ret;
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}
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/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
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static int wait_for_fpga_config(void)
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{
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int ret = 0, done;
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/* approx 5 s */
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u32 timeout = 500000;
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printf("PCIe FPGA config:");
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do {
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done = qrio_get_gpio(GPIO_A, FPGA_DONE);
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if (timeout-- == 0) {
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printf(" FPGA_DONE timeout\n");
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ret = -EFAULT;
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goto err_out;
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}
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udelay(10);
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} while (!done);
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printf(" done\n");
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err_out:
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/* deactive CONF_SEL and give the CPU conf EEPROM access */
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qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
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toggle_fpga_eeprom_bus(true);
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return ret;
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}
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#define PCIE_SW_RST 14
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#define PEXHC_RST 13
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#define HOOPER_RST 12
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void pci_init_board(void)
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{
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qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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/* wait for the PCIe FPGA to be configured
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* it has been triggered earlier in board_early_init_r */
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if (wait_for_fpga_config())
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printf("error finishing PCIe FPGA config\n");
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qrio_prst(PCIE_SW_RST, false, false);
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qrio_prst(PEXHC_RST, false, false);
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qrio_prst(HOOPER_RST, false, false);
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/* Hooper is not direcly PCIe capable */
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mdelay(50);
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fsl_pcie_init_board(0);
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}
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void pci_of_setup(void *blob, bd_t *bd)
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{
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FT_FSL_PCI_SETUP;
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}
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