mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 06:43:45 +09:00
d4ad111dc4
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
55 lines
1.2 KiB
Makefile
55 lines
1.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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# Copyright 2016-2018 NXP
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# Copyright 2014-2015, Freescale Semiconductor
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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endif
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obj-$(CONFIG_SPL) += spl.o
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obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
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ifneq ($(CONFIG_FSL_LSCH3),)
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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else
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ifneq ($(CONFIG_FSL_LSCH2),)
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obj-y += fsl_lsch2_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
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endif
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endif
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ifneq ($(CONFIG_ARCH_LX2160A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1043A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
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obj-y += icid.o ls1043_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS1012A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1046A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
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obj-y += icid.o ls1046_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS1088A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1028A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
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endif
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