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https://github.com/brain-hackers/u-boot-brain
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ba39608147
DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
747 lines
16 KiB
C
747 lines
16 KiB
C
/*
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* Timing and Organization details of the ddr device parts used in OMAP5
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* EVM
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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/*
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* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
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* EVM. Since the parts used and geometry are identical for
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* evm for a given OMAP5 revision, this information is kept
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* here instead of being in board directory. However the key functions
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* exported are weakly linked so that they can be over-ridden in the board
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* directory if there is a OMAP5 board in the future that uses a different
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* memory device or geometry.
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*
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* For any new board with different memory devices over-ride one or more
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* of the following functions as per the CONFIG flags you intend to enable:
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* - emif_get_reg_dump()
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* - emif_get_dmm_regs()
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* - emif_get_device_details()
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* - emif_get_device_timings()
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*/
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#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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const struct emif_regs emif_regs_532_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000081A,
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.sdram_tim1 = 0x772F6873,
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.sdram_tim2 = 0x304a129a,
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.sdram_tim3 = 0x02f7e45f,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
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.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
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.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000081A,
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.sdram_tim1 = 0x772F6873,
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.sdram_tim2 = 0x304a129a,
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.sdram_tim3 = 0x02f7e45f,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x100b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E30400d,
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.emif_ddr_phy_ctlr_1 = 0x0E30400d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
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.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
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.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
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.emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
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};
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const struct emif_regs emif_regs_266_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000040D,
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.sdram_tim1 = 0x2A86B419,
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.sdram_tim2 = 0x1025094A,
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.sdram_tim3 = 0x026BA22F,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
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.emif_ddr_ext_phy_ctrl_3 = 0x14829052,
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.emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.sdram_config2 = 0x0,
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.ref_ctrl = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0020420A,
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.emif_ddr_phy_ctlr_1 = 0x0024420A,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.sdram_config2 = 0x0,
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.ref_ctrl = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x1007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0030400A,
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.emif_ddr_phy_ctlr_1 = 0x0034400A,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x40000305
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};
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const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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*regs = &emif_regs_532_mhz_2cs;
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break;
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case OMAP5432_ES1_0:
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*regs = &emif_regs_ddr3_532_mhz_1cs;
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break;
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case OMAP5430_ES2_0:
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*regs = &emif_regs_532_mhz_2cs_es2;
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break;
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case OMAP5432_ES2_0:
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default:
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*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
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break;
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}
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}
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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__attribute__((weak, alias("emif_get_reg_dump_sdp")));
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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case OMAP5430_ES2_0:
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case OMAP5432_ES1_0:
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case OMAP5432_ES2_0:
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default:
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*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
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break;
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}
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
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#else
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static const struct lpddr2_device_details dev_4G_S4_details = {
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.type = LPDDR2_TYPE_S4,
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.density = LPDDR2_DENSITY_4Gb,
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.io_width = LPDDR2_IO_WIDTH_32,
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.manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
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};
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static void emif_get_device_details_sdp(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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{
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/* EMIF1 & EMIF2 have identical configuration */
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*cs0_device_details = dev_4G_S4_details;
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*cs1_device_details = dev_4G_S4_details;
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}
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void emif_get_device_details(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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__attribute__((weak, alias("emif_get_device_details_sdp")));
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#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
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const u32 ext_phy_ctrl_const_base[] = {
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0x01004010,
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0x00001004,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000001,
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0x540A8150,
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0xA81502a0,
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0x002A0540,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000077,
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0x0
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};
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const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
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0x01004010,
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0x00001004,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000002,
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0x0,
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0x0,
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0x0,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000057,
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0x0
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};
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const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
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0x50D4350D,
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0x00000D43,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000002,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000057,
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00330033,
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0x00330033,
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0x002F002F,
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0x00320032,
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0x00310031,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00520052,
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0x00520052,
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0x00470047,
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0x00490049,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
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0x10040100,
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0x00A400A4,
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0x00A900A9,
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0x00B000B0,
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0x00B000B0,
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0x00A400A4,
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0x00390039,
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0x00320032,
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0x00320032,
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0x00320032,
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0x00440044,
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0x00550055,
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0x00550055,
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0x00550055,
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0x00550055,
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0x007F007F,
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0x004D004D,
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0x00430043,
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0x00560056,
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0x00540054,
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0x00600060,
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0x0,
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0x00600020,
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0x40010080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
|
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0x0,
|
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0x0,
|
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0x0,
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0x0,
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0x0,
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0x0
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};
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const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
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0x04040100,
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0x006B009F,
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0x006B00A2,
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0x006B00A8,
|
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0x006B00A8,
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0x006B00B2,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x00600073,
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0x00600071,
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0x0060007C,
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0x0060007E,
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0x00600084,
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0x00400053,
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0x00400051,
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0x0040005C,
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0x0040005E,
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0x00400064,
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0x00800080,
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0x00800080,
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0x40010080,
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0x08102040,
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0x005B008F,
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0x005B0092,
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0x005B0098,
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0x005B0098,
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0x005B00A2,
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0x00300043,
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0x00300041,
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0x0030004C,
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0x0030004E,
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0x00300054,
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0x00000077
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};
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const struct lpddr2_mr_regs mr_regs = {
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr2 = 0x6,
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.mr3 = 0x1,
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.mr10 = MR10_ZQ_ZQINIT,
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.mr16 = MR16_REF_FULL_ARRAY
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};
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|
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void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
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const u32 **regs,
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u32 *size)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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case OMAP5430_ES2_0:
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*regs = ext_phy_ctrl_const_base;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
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break;
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case OMAP5432_ES1_0:
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*regs = ddr3_ext_phy_ctrl_const_base_es1;
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
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break;
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case OMAP5432_ES2_0:
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
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|
break;
|
|
case DRA752_ES1_0:
|
|
case DRA752_ES1_1:
|
|
case DRA752_ES2_0:
|
|
if (emif_nr == 1) {
|
|
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
|
|
*size =
|
|
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
|
|
} else {
|
|
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
|
|
*size =
|
|
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
|
|
}
|
|
break;
|
|
case DRA722_ES1_0:
|
|
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
|
|
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
|
|
break;
|
|
case DRA762_ES1_0:
|
|
case DRA722_ES2_0:
|
|
case DRA722_ES2_1:
|
|
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
|
|
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
|
|
break;
|
|
default:
|
|
*regs = ddr3_ext_phy_ctrl_const_base_es2;
|
|
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
|
|
|
|
}
|
|
}
|
|
|
|
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
|
|
{
|
|
*regs = &mr_regs;
|
|
}
|
|
|
|
static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
|
|
{
|
|
u32 *ext_phy_ctrl_base = 0;
|
|
u32 *emif_ext_phy_ctrl_base = 0;
|
|
u32 emif_nr;
|
|
const u32 *ext_phy_ctrl_const_regs;
|
|
u32 i = 0;
|
|
u32 size;
|
|
|
|
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
|
|
|
|
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
|
|
|
|
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
|
|
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
|
|
|
|
/* Configure external phy control timing registers */
|
|
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
|
|
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
|
|
/* Update shadow registers */
|
|
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
|
|
}
|
|
|
|
/*
|
|
* external phy 6-24 registers do not change with
|
|
* ddr frequency
|
|
*/
|
|
emif_get_ext_phy_ctrl_const_regs(emif_nr,
|
|
&ext_phy_ctrl_const_regs, &size);
|
|
|
|
for (i = 0; i < size; i++) {
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
emif_ext_phy_ctrl_base++);
|
|
/* Update shadow registers */
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
emif_ext_phy_ctrl_base++);
|
|
}
|
|
}
|
|
|
|
static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
|
|
{
|
|
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
|
|
u32 *emif_ext_phy_ctrl_base = 0;
|
|
u32 emif_nr;
|
|
const u32 *ext_phy_ctrl_const_regs;
|
|
u32 i, hw_leveling, size, phy;
|
|
|
|
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
|
|
|
|
hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
|
|
phy = regs->emif_ddr_phy_ctlr_1_init;
|
|
|
|
emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
|
|
|
|
emif_get_ext_phy_ctrl_const_regs(emif_nr,
|
|
&ext_phy_ctrl_const_regs, &size);
|
|
|
|
writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
|
|
writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
|
|
|
|
/*
|
|
* Copy the predefined PHY register values
|
|
* if leveling is disabled.
|
|
*/
|
|
if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
|
|
for (i = 1; i < 6; i++) {
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2]);
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2 + 1]);
|
|
}
|
|
|
|
if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
|
|
for (i = 6; i < 11; i++) {
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2]);
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2 + 1]);
|
|
}
|
|
|
|
if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
|
|
for (i = 11; i < 25; i++) {
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2]);
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2 + 1]);
|
|
}
|
|
|
|
if (hw_leveling) {
|
|
/*
|
|
* Write the init value for HW levling to occur
|
|
*/
|
|
for (i = 21; i < 35; i++) {
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2]);
|
|
writel(ext_phy_ctrl_const_regs[i],
|
|
&emif_ext_phy_ctrl_base[i * 2 + 1]);
|
|
}
|
|
}
|
|
}
|
|
|
|
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
|
|
{
|
|
if (is_omap54xx())
|
|
do_ext_phy_settings_omap5(base, regs);
|
|
else
|
|
do_ext_phy_settings_dra7(base, regs);
|
|
}
|
|
|
|
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
|
|
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
|
|
.max_freq = 532000000,
|
|
.RL = 8,
|
|
.tRPab = 21,
|
|
.tRCD = 18,
|
|
.tWR = 15,
|
|
.tRASmin = 42,
|
|
.tRRD = 10,
|
|
.tWTRx2 = 15,
|
|
.tXSR = 140,
|
|
.tXPx2 = 15,
|
|
.tRFCab = 130,
|
|
.tRTPx2 = 15,
|
|
.tCKE = 3,
|
|
.tCKESR = 15,
|
|
.tZQCS = 90,
|
|
.tZQCL = 360,
|
|
.tZQINIT = 1000,
|
|
.tDQSCKMAXx2 = 11,
|
|
.tRASmax = 70,
|
|
.tFAW = 50
|
|
};
|
|
|
|
static const struct lpddr2_min_tck min_tck = {
|
|
.tRL = 3,
|
|
.tRP_AB = 3,
|
|
.tRCD = 3,
|
|
.tWR = 3,
|
|
.tRAS_MIN = 3,
|
|
.tRRD = 2,
|
|
.tWTR = 2,
|
|
.tXP = 2,
|
|
.tRTP = 2,
|
|
.tCKE = 3,
|
|
.tCKESR = 3,
|
|
.tFAW = 8
|
|
};
|
|
|
|
static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
|
|
&timings_jedec_532_mhz
|
|
};
|
|
|
|
static const struct lpddr2_device_timings dev_4G_S4_timings = {
|
|
.ac_timings = ac_timings,
|
|
.min_tck = &min_tck,
|
|
};
|
|
|
|
/*
|
|
* List of status registers to be controlled back to control registers
|
|
* after initial leveling
|
|
* readreg, writereg
|
|
*/
|
|
const struct read_write_regs omap5_bug_00339_regs[] = {
|
|
{ 8, 5 },
|
|
{ 9, 6 },
|
|
{ 10, 7 },
|
|
{ 14, 8 },
|
|
{ 15, 9 },
|
|
{ 16, 10 },
|
|
{ 11, 2 },
|
|
{ 12, 3 },
|
|
{ 13, 4 },
|
|
{ 17, 11 },
|
|
{ 18, 12 },
|
|
{ 19, 13 },
|
|
};
|
|
|
|
const struct read_write_regs dra_bug_00339_regs[] = {
|
|
{ 7, 7 },
|
|
{ 8, 8 },
|
|
{ 9, 9 },
|
|
{ 10, 10 },
|
|
{ 11, 11 },
|
|
{ 12, 2 },
|
|
{ 13, 3 },
|
|
{ 14, 4 },
|
|
{ 15, 5 },
|
|
{ 16, 6 },
|
|
{ 17, 12 },
|
|
{ 18, 13 },
|
|
{ 19, 14 },
|
|
{ 20, 15 },
|
|
{ 21, 16 },
|
|
{ 22, 17 },
|
|
{ 23, 18 },
|
|
{ 24, 19 },
|
|
{ 25, 20 },
|
|
{ 26, 21}
|
|
};
|
|
|
|
const struct read_write_regs *get_bug_regs(u32 *iterations)
|
|
{
|
|
const struct read_write_regs *bug_00339_regs_ptr = NULL;
|
|
|
|
switch (omap_revision()) {
|
|
case OMAP5430_ES1_0:
|
|
case OMAP5430_ES2_0:
|
|
case OMAP5432_ES1_0:
|
|
case OMAP5432_ES2_0:
|
|
bug_00339_regs_ptr = omap5_bug_00339_regs;
|
|
*iterations = sizeof(omap5_bug_00339_regs)/
|
|
sizeof(omap5_bug_00339_regs[0]);
|
|
break;
|
|
case DRA762_ES1_0:
|
|
case DRA752_ES1_0:
|
|
case DRA752_ES1_1:
|
|
case DRA752_ES2_0:
|
|
case DRA722_ES1_0:
|
|
case DRA722_ES2_0:
|
|
case DRA722_ES2_1:
|
|
bug_00339_regs_ptr = dra_bug_00339_regs;
|
|
*iterations = sizeof(dra_bug_00339_regs)/
|
|
sizeof(dra_bug_00339_regs[0]);
|
|
break;
|
|
default:
|
|
printf("\n Error: UnKnown SOC");
|
|
}
|
|
|
|
return bug_00339_regs_ptr;
|
|
}
|
|
|
|
void emif_get_device_timings_sdp(u32 emif_nr,
|
|
const struct lpddr2_device_timings **cs0_device_timings,
|
|
const struct lpddr2_device_timings **cs1_device_timings)
|
|
{
|
|
/* Identical devices on EMIF1 & EMIF2 */
|
|
*cs0_device_timings = &dev_4G_S4_timings;
|
|
*cs1_device_timings = &dev_4G_S4_timings;
|
|
}
|
|
|
|
void emif_get_device_timings(u32 emif_nr,
|
|
const struct lpddr2_device_timings **cs0_device_timings,
|
|
const struct lpddr2_device_timings **cs1_device_timings)
|
|
__attribute__((weak, alias("emif_get_device_timings_sdp")));
|
|
|
|
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
|