mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 13:16:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
283 lines
8.1 KiB
C
283 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*/
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#ifndef __ASM_ARC_IO_H
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#define __ASM_ARC_IO_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#ifdef __ARCHS__
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/*
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* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
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* due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
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*
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* Explicit barrier provided by DMB instruction
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* - Operand supports fine grained load/store/load+store semantics
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* - Ensures that selected memory operation issued before it will complete
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* before any subsequent memory operation of same type
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* - DMB guarantees SMP as well as local barrier semantics
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* (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
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* UP: barrier(), SMP: smp_*mb == *mb)
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* - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
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* in the general case. Plus it only provides full barrier.
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*/
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#define mb() asm volatile("dmb 3\n" : : : "memory")
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#define rmb() asm volatile("dmb 1\n" : : : "memory")
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#define wmb() asm volatile("dmb 2\n" : : : "memory")
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#else
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/*
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* ARCompact based cores (ARC700) only have SYNC instruction which is super
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* heavy weight as it flushes the pipeline as well.
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* There are no real SMP implementations of such cores.
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*/
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#define mb() asm volatile("sync\n" : : : "memory")
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#endif
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#ifdef __ARCHS__
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() asm volatile("" : : : "memory")
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#define __iowmb() asm volatile("" : : : "memory")
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#endif
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static inline void sync(void)
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{
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/* Not yet implemented */
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}
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 b;
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__asm__ __volatile__("ldb%U1 %0, %1\n"
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: "=r" (b)
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: "m" (*(volatile u8 __force *)addr)
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: "memory");
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return b;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 s;
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__asm__ __volatile__("ldw%U1 %0, %1\n"
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: "=r" (s)
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: "m" (*(volatile u16 __force *)addr)
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: "memory");
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return s;
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 w;
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__asm__ __volatile__("ld%U1 %0, %1\n"
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: "=r" (w)
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: "m" (*(volatile u32 __force *)addr)
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: "memory");
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return w;
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}
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stb%U1 %0, %1\n"
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:
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: "r" (b), "m" (*(volatile u8 __force *)addr)
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: "memory");
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}
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static inline void __raw_writew(u16 s, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stw%U1 %0, %1\n"
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:
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: "r" (s), "m" (*(volatile u16 __force *)addr)
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: "memory");
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}
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static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("st%U1 %0, %1\n"
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:
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: "r" (w), "m" (*(volatile u32 __force *)addr)
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: "memory");
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}
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static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stb.ab r8, [r1, 1]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stw.ab r8, [r1, 2]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab r8, [r1, 4]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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/*
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* MMIO can also get buffered/optimized in micro-arch, so barriers needed
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* Based on ARM model for the typical use case
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*
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* <ST [DMA buffer]>
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* <writel MMIO "go" reg>
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* or:
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* <readl MMIO "status" reg>
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* <LD [DMA buffer]>
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*
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* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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/*
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* Relaxed API for drivers which can handle barrier ordering themselves
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*
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* Also these are defined to perform little endian accesses.
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* To provide the typical device register semantics of fixed endian,
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* swap the byte order for Big Endian
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*
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* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
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#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
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#define out_le32(a, v) out_arch(l, le32, a, v)
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#define out_le16(a, v) out_arch(w, le16, a, v)
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#define in_le32(a) in_arch(l, le32, a)
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#define in_le16(a) in_arch(w, le16, a)
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#define out_be32(a, v) out_arch(l, be32, a, v)
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#define out_be16(a, v) out_arch(w, be16, a, v)
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#define in_be32(a) in_arch(l, be32, a)
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#define in_be16(a) in_arch(w, be16, a)
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#define out_8(a, v) __raw_writeb(v, a)
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#define in_8(a) __raw_readb(a)
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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* set multiple bits in a register using a single call. These macros can
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* also be used to set a multiple-bit bit pattern using a mask, by
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* specifying the mask in the 'clear' parameter and the new bit pattern
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* in the 'set' parameter.
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*/
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#define clrbits(type, addr, clear) \
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out_##type((addr), in_##type(addr) & ~(clear))
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#define setbits(type, addr, set) \
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out_##type((addr), in_##type(addr) | (set))
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#define clrsetbits(type, addr, clear, set) \
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out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
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#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
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#define setbits_be32(addr, set) setbits(be32, addr, set)
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#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
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#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
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#define setbits_le32(addr, set) setbits(le32, addr, set)
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#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
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#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
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#define setbits_be16(addr, set) setbits(be16, addr, set)
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#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
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#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
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#define setbits_le16(addr, set) setbits(le16, addr, set)
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#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
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#define clrbits_8(addr, clear) clrbits(8, addr, clear)
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#define setbits_8(addr, set) setbits(8, addr, set)
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#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
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#include <asm-generic/io.h>
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#endif /* __ASM_ARC_IO_H */
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