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u-boot-brain/board/freescale/t4qds
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Stephen George 49e946cb6a board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M 
Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
..
ddr.c powerpc/t4240qds: Update DDR timing table 2013-05-14 16:00:27 -05:00
eth.c T4240/eth: fix SGMII card PHY address 2013-05-14 16:13:25 -05:00
law.c board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M 2013-05-24 16:54:12 -05:00
Makefile powerpc/t4qds: Add T4QDS board 2012-10-22 15:52:46 -05:00
pci.c powerpc/t4qds: Add T4QDS board 2012-10-22 15:52:46 -05:00
t4_pbi.cfg T4240/ramboot: enable PBL tool for T4240 2013-05-24 16:54:10 -05:00
t4_rcw.cfg T4240/ramboot: enable PBL tool for T4240 2013-05-24 16:54:10 -05:00
t4qds.c powerpc/t4qds: use clock measurement for sysclk and ddr clock 2013-05-24 16:54:12 -05:00
t4qds.h powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c 2013-01-30 11:25:08 -06:00
t4240qds_qixis.h powerpc/t4qds: Fix disabling remote I2C connection 2013-05-14 16:13:25 -05:00
tlb.c board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M 2013-05-24 16:54:12 -05:00