mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
553f09823c
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be some end address; to make the meaning more clear we rename it into CONFIG_SYS_INIT_RAM_SIZE No other code changes are performed in this patch, only minor editing of white space (due to the changed length) and the comments was done, where noticed. Note that the code for the PATI and cmi_mpc5xx board configurations looks seriously broken. Last known maintainers on Cc: Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Denis Peter <d.peter@mpl.ch> Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch> Acked-by: Kumar Gala <galak@kernel.crashing.org>
296 lines
7.8 KiB
C
296 lines
7.8 KiB
C
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2010
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* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <version.h>
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#define CONFIG_MPC5xxx 1
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#define CONFIG_MPC5200 1
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFF800000
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#endif
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CACHELINE_SHIFT 5
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#endif
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#define CONFIG_PSC_CONSOLE 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
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230400}
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#undef CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_SYS_XLB_PIPELINING 1
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#define CONFIG_HIGH_BATS 1
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#define MV_CI mvSMR
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#define MV_VCI mvSMR
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#define MV_FPGA_DATA 0xff840000
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#define MV_FPGA_SIZE 0x1ff88
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#define MV_KERNEL_ADDR 0xfff00000
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#define MV_SCRIPT_ADDR 0xff806000
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#define MV_INITRD_ADDR 0xff880000
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#define MV_INITRD_LENGTH 0x00240000
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#define MV_SCRATCH_ADDR 0xffcc0000
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#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define MV_KERNEL_ADDR_RAM 0x00100000
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#define MV_INITRD_ADDR_RAM 0x00400000
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/*
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* Supported commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SDRAM
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_RANDOM_DELAY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_VENDOREX
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/*
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* Autoboot
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*/
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_BOOTCOMMAND "source ${script_addr}"
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#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
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" allocate=6M"
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#define XMK_STR(x) #x
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#define MK_STR(x) XMK_STR(x)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console_nr=0\0" \
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"console=no\0" \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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"fpga=0\0" \
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"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
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"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
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"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
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"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
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"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
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"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
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"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
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"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
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"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
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"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
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"mv_version=" U_BOOT_VERSION "\0" \
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"dhcp_client_id=" MK_STR(MV_CI) "\0" \
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"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
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"netretry=no\0" \
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"use_static_ipaddr=no\0" \
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"static_ipaddr=192.168.0.101\0" \
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"static_netmask=255.255.255.0\0" \
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"static_gateway=0.0.0.0\0" \
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"initrd_name=uInitrd.mvsmr-rfs\0" \
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"zcip=yes\0" \
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"netboot=no\0" \
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""
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#undef XMK_STR
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#undef MK_STR
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
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/*
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* Flash configuration
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*/
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#undef CONFIG_FLASH_16BIT
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_LOWBOOT
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_FLASH_SIZE 0x00800000
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_ENV_OFFSET 0x8000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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/* used by linker script to wrap code around */
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#define CONFIG_SCRIPT_OFFSET 0x6000
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#define CONFIG_SCRIPT_SECT_SIZE 0x2000
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT 1
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MALLOC_LEN (512 << 10)
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_MODULE 1
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#define CONFIG_SYS_I2C_SPEED 86000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* Ethernet configuration
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*/
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_MPC5xxx_FEC
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_NETDEV eth0
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#undef CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CBSIZE 1024
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#else
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#define CONFIG_SYS_CBSIZE 256
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00800000
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#define CONFIG_SYS_MEMTEST_END 0x02f00000
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#define CONFIG_SYS_HZ 1000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x02000000
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 0x00200000
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
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#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x00047800
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS_BURST 0x000000f0
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
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#define CONFIG_SYS_RESET_ADDRESS 0x00000100
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#undef FPGA_DEBUG
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#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
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#define CONFIG_FPGA_XILINX 1
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#define CONFIG_FPGA_SPARTAN2 1
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#define CONFIG_FPGA_COUNT 1
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#endif
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