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3e747197b1
The sdram controller blocks are very similar to the rk3288 in utilizing memory scheduler, Designware uPCTL and Designware PUBL blocks, only limited to one bank instead of two. There are some minimal differences when setting up the ram, so it gets a separate driver for the rk3188 but reuses the driver structs, as there is no need to define the same again. More optimization can happen when the modelling of the controller parts in the dts actually follow the hardware layout hopefully at some point in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
26 lines
398 B
C
26 lines
398 B
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_DDR_RK3188_H
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#define _ASM_ARCH_DDR_RK3188_H
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#include <asm/arch/ddr_rk3288.h>
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/*
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* RK3188 Memory scheduler register map.
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*/
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struct rk3188_msch {
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u32 coreid;
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u32 revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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};
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check_member(rk3188_msch, readlatency, 0x0014);
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#endif
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