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https://github.com/brain-hackers/u-boot-brain
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35f21c3ac6
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
92 lines
2.3 KiB
Plaintext
92 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am654.dtsi"
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#include <dt-bindings/pinctrl/k3.h>
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/ {
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compatible = "ti,am654-evm", "ti,am654";
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model = "Texas Instruments AM654 Base Board";
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "earlycon=ns16550a,mmio32,0x02800000";
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};
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aliases {
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remoteproc0 = &mcu_r5fss0_core0;
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remoteproc1 = &mcu_r5fss0_core1;
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};
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memory@80000000 {
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device_type = "memory";
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/* 4G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure_ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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};
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&main_pmx0 {
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main_mmc0_pins_default: main_mmc0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
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AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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};
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&wkup_pmx0 {
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
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AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
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>;
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};
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};
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&sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc0_pins_default>;
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bus-width = <8>;
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non-removable;
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ti,driver-strength-ohm = <50>;
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};
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&wkup_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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tca9554: gpio@38 {
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compatible = "nxp,pca9554";
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reg = <0x38>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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