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![Lad Prabhakar](/assets/img/avatar_default.png)
Drop unused members from struct sh_pfc_pinctrl. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
997 lines
23 KiB
C
997 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Pin Control driver for SuperH Pin Function Controller.
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*
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* Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
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*
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2009 - 2012 Paul Mundt
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* Copyright (C) 2017 Marek Vasut
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*/
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#define DRV_NAME "sh-pfc"
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "sh_pfc.h"
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enum sh_pfc_model {
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SH_PFC_R8A7790 = 0,
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SH_PFC_R8A7791,
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SH_PFC_R8A7792,
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SH_PFC_R8A7793,
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SH_PFC_R8A7794,
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SH_PFC_R8A7795,
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SH_PFC_R8A7796,
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SH_PFC_R8A774A1,
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SH_PFC_R8A774B1,
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SH_PFC_R8A774E1,
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SH_PFC_R8A77965,
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SH_PFC_R8A77970,
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SH_PFC_R8A77980,
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SH_PFC_R8A77990,
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SH_PFC_R8A77995,
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};
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struct sh_pfc_pin_config {
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u32 type;
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};
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struct sh_pfc_pinctrl {
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struct sh_pfc *pfc;
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struct sh_pfc_pin_config *configs;
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};
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struct sh_pfc_pin_range {
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u16 start;
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u16 end;
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};
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struct sh_pfc_pinctrl_priv {
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struct sh_pfc pfc;
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struct sh_pfc_pinctrl pmx;
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};
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
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{
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unsigned int offset;
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unsigned int i;
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for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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if (pin <= range->end)
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return pin >= range->start
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? offset + pin - range->start : -1;
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offset += range->end - range->start + 1;
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}
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return -EINVAL;
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}
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static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
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{
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if (enum_id < r->begin)
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return 0;
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if (enum_id > r->end)
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return 0;
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return 1;
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}
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u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
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{
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switch (reg_width) {
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case 8:
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return readb(mapped_reg);
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case 16:
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return readw(mapped_reg);
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case 32:
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return readl(mapped_reg);
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}
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BUG();
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return 0;
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}
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
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u32 data)
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{
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switch (reg_width) {
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case 8:
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writeb(data, mapped_reg);
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return;
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case 16:
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writew(data, mapped_reg);
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return;
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case 32:
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writel(data, mapped_reg);
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return;
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}
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BUG();
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}
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u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
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{
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return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
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}
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void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
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{
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
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sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int in_pos,
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void __iomem **mapped_regp, u32 *maskp,
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unsigned int *posp)
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{
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unsigned int k;
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*mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
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if (crp->field_width) {
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*maskp = (1 << crp->field_width) - 1;
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*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
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} else {
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*maskp = (1 << crp->var_field_width[in_pos]) - 1;
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*posp = crp->reg_width;
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for (k = 0; k <= in_pos; k++)
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*posp -= crp->var_field_width[k];
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}
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}
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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int field, u32 value)
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{
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void __iomem *mapped_reg;
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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unsigned int pos;
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u32 mask, data;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
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"r_width = %u, f_width = %u\n",
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crp->reg, value, field, crp->reg_width, crp->field_width);
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mask = ~(mask << pos);
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value = value << pos;
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data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
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data &= mask;
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data |= value;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
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const struct pinmux_cfg_reg **crp,
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unsigned int *fieldp, u32 *valuep)
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{
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unsigned int k = 0;
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while (1) {
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const struct pinmux_cfg_reg *config_reg =
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pfc->info->cfg_regs + k;
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unsigned int r_width = config_reg->reg_width;
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unsigned int f_width = config_reg->field_width;
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unsigned int curr_width;
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unsigned int bit_pos;
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unsigned int pos = 0;
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unsigned int m = 0;
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if (!r_width)
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break;
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for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
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u32 ncomb;
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u32 n;
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if (f_width)
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curr_width = f_width;
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else
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curr_width = config_reg->var_field_width[m];
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ncomb = 1 << curr_width;
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for (n = 0; n < ncomb; n++) {
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if (config_reg->enum_ids[pos + n] == enum_id) {
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*crp = config_reg;
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*fieldp = m;
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*valuep = n;
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return 0;
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}
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}
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pos += ncomb;
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m++;
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}
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k++;
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}
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return -EINVAL;
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}
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static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
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u16 *enum_idp)
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{
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const u16 *data = pfc->info->pinmux_data;
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unsigned int k;
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if (pos) {
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*enum_idp = data[pos + 1];
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return pos + 1;
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}
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for (k = 0; k < pfc->info->pinmux_data_size; k++) {
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if (data[k] == mark) {
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*enum_idp = data[k + 1];
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return k + 1;
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}
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}
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dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
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mark);
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return -EINVAL;
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}
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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{
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const struct pinmux_range *range;
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int pos = 0;
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switch (pinmux_type) {
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case PINMUX_TYPE_GPIO:
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case PINMUX_TYPE_FUNCTION:
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range = NULL;
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break;
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case PINMUX_TYPE_OUTPUT:
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range = &pfc->info->output;
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break;
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case PINMUX_TYPE_INPUT:
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range = &pfc->info->input;
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break;
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default:
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return -EINVAL;
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}
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/* Iterate over all the configuration fields we need to update. */
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while (1) {
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const struct pinmux_cfg_reg *cr;
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unsigned int field;
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u16 enum_id;
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u32 value;
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int in_range;
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int ret;
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pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
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if (pos < 0)
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return pos;
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if (!enum_id)
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break;
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/* Check if the configuration field selects a function. If it
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* doesn't, skip the field if it's not applicable to the
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* requested pinmux type.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
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if (!in_range) {
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if (pinmux_type == PINMUX_TYPE_FUNCTION) {
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/* Functions are allowed to modify all
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* fields.
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*/
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in_range = 1;
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} else if (pinmux_type != PINMUX_TYPE_GPIO) {
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/* Input/output types can only modify fields
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* that correspond to their respective ranges.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, range);
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/*
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* special case pass through for fixed
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* input-only or output-only pins without
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* function enum register association.
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*/
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if (in_range && enum_id == range->force)
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continue;
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}
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/* GPIOs are only allowed to modify function fields. */
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}
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if (!in_range)
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continue;
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ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
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if (ret < 0)
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return ret;
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sh_pfc_write_config_reg(pfc, cr, field, value);
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}
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return 0;
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}
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const struct pinmux_bias_reg *
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sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *bit)
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{
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unsigned int i, j;
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
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if (pfc->info->bias_regs[i].pins[j] == pin) {
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*bit = j;
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return &pfc->info->bias_regs[i];
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}
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}
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}
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WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
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return NULL;
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}
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static int sh_pfc_init_ranges(struct sh_pfc *pfc)
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{
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struct sh_pfc_pin_range *range;
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unsigned int nr_ranges;
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unsigned int i;
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if (pfc->info->pins[0].pin == (u16)-1) {
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/* Pin number -1 denotes that the SoC doesn't report pin numbers
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* in its pin arrays yet. Consider the pin numbers range as
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* continuous and allocate a single range.
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*/
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pfc->nr_ranges = 1;
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pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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pfc->ranges->start = 0;
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pfc->ranges->end = pfc->info->nr_pins - 1;
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pfc->nr_gpio_pins = pfc->info->nr_pins;
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return 0;
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}
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/* Count, allocate and fill the ranges. The PFC SoC data pins array must
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* be sorted by pin numbers, and pins without a GPIO port must come
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* last.
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*/
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for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
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nr_ranges++;
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}
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pfc->nr_ranges = nr_ranges;
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pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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range = pfc->ranges;
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range->start = pfc->info->pins[0].pin;
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for (i = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
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continue;
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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range++;
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range->start = pfc->info->pins[i].pin;
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}
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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return 0;
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}
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static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->nr_pins;
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}
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static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->pins[selector].name;
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}
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static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->nr_groups;
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}
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static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->groups[selector].name;
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}
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static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->nr_functions;
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}
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static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->pfc.info->functions[selector].name;
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}
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static int sh_pfc_gpio_request_enable(struct udevice *dev,
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unsigned pin_selector)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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struct sh_pfc_pinctrl *pmx = &priv->pmx;
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struct sh_pfc *pfc = &priv->pfc;
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struct sh_pfc_pin_config *cfg;
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const struct sh_pfc_pin *pin = NULL;
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int i, ret, idx;
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for (i = 0; i < pfc->info->nr_pins; i++) {
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if (priv->pfc.info->pins[i].pin != pin_selector)
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continue;
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pin = &priv->pfc.info->pins[i];
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break;
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}
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if (!pin)
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return -EINVAL;
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idx = sh_pfc_get_pin_index(pfc, pin->pin);
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cfg = &pmx->configs[idx];
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if (cfg->type != PINMUX_TYPE_NONE)
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return -EBUSY;
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ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
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if (ret)
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return ret;
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cfg->type = PINMUX_TYPE_GPIO;
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return 0;
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}
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static int sh_pfc_gpio_disable_free(struct udevice *dev,
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unsigned pin_selector)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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struct sh_pfc_pinctrl *pmx = &priv->pmx;
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struct sh_pfc *pfc = &priv->pfc;
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struct sh_pfc_pin_config *cfg;
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const struct sh_pfc_pin *pin = NULL;
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int i, idx;
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for (i = 0; i < pfc->info->nr_pins; i++) {
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if (priv->pfc.info->pins[i].pin != pin_selector)
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continue;
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pin = &priv->pfc.info->pins[i];
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break;
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}
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if (!pin)
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return -EINVAL;
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|
|
idx = sh_pfc_get_pin_index(pfc, pin->pin);
|
|
cfg = &pmx->configs[idx];
|
|
|
|
cfg->type = PINMUX_TYPE_NONE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
|
|
unsigned func_selector)
|
|
{
|
|
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
|
struct sh_pfc_pinctrl *pmx = &priv->pmx;
|
|
struct sh_pfc *pfc = &priv->pfc;
|
|
const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
|
|
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
|
|
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
|
|
|
|
if (cfg->type != PINMUX_TYPE_NONE)
|
|
return -EBUSY;
|
|
|
|
return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
|
|
}
|
|
|
|
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
|
|
unsigned func_selector)
|
|
{
|
|
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
|
struct sh_pfc_pinctrl *pmx = &priv->pmx;
|
|
struct sh_pfc *pfc = &priv->pfc;
|
|
const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
|
|
unsigned int i;
|
|
int ret = 0;
|
|
|
|
for (i = 0; i < grp->nr_pins; ++i) {
|
|
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
|
|
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
|
|
|
|
if (cfg->type != PINMUX_TYPE_NONE) {
|
|
ret = -EBUSY;
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < grp->nr_pins; ++i) {
|
|
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
|
|
if (ret < 0)
|
|
break;
|
|
}
|
|
|
|
done:
|
|
return ret;
|
|
}
|
|
#if CONFIG_IS_ENABLED(PINCONF)
|
|
static const struct pinconf_param sh_pfc_pinconf_params[] = {
|
|
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
|
|
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
|
|
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
|
|
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
|
|
{ "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
|
|
};
|
|
|
|
static void __iomem *
|
|
sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
|
|
unsigned int *offset, unsigned int *size)
|
|
{
|
|
const struct pinmux_drive_reg_field *field;
|
|
const struct pinmux_drive_reg *reg;
|
|
unsigned int i;
|
|
|
|
for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
|
|
for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
|
|
field = ®->fields[i];
|
|
|
|
if (field->size && field->pin == pin) {
|
|
*offset = field->offset;
|
|
*size = field->size;
|
|
|
|
return (void __iomem *)(uintptr_t)reg->reg;
|
|
}
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
|
|
unsigned int pin, u16 strength)
|
|
{
|
|
unsigned int offset;
|
|
unsigned int size;
|
|
unsigned int step;
|
|
void __iomem *reg;
|
|
void __iomem *unlock_reg =
|
|
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
|
|
u32 val;
|
|
|
|
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
|
|
if (!reg)
|
|
return -EINVAL;
|
|
|
|
step = size == 2 ? 6 : 3;
|
|
|
|
if (strength < step || strength > 24)
|
|
return -EINVAL;
|
|
|
|
/* Convert the value from mA based on a full drive strength value of
|
|
* 24mA. We can make the full value configurable later if needed.
|
|
*/
|
|
strength = strength / step - 1;
|
|
|
|
val = sh_pfc_read_raw_reg(reg, 32);
|
|
val &= ~GENMASK(offset + 4 - 1, offset);
|
|
val |= strength << offset;
|
|
|
|
if (unlock_reg)
|
|
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
|
|
|
|
sh_pfc_write_raw_reg(reg, 32, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Check whether the requested parameter is supported for a pin. */
|
|
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
|
|
unsigned int param)
|
|
{
|
|
int idx = sh_pfc_get_pin_index(pfc, _pin);
|
|
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
return pin->configs &
|
|
(SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
|
|
|
|
case PIN_CONFIG_POWER_SOURCE:
|
|
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
|
|
unsigned int param, unsigned int arg)
|
|
{
|
|
struct sh_pfc *pfc = pmx->pfc;
|
|
void __iomem *pocctrl;
|
|
void __iomem *unlock_reg =
|
|
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
|
|
u32 addr, val;
|
|
int bit, ret;
|
|
|
|
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
|
|
return -ENOTSUPP;
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
if (!pfc->info->ops || !pfc->info->ops->set_bias)
|
|
return -ENOTSUPP;
|
|
|
|
pfc->info->ops->set_bias(pfc, _pin, param);
|
|
|
|
break;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
break;
|
|
|
|
case PIN_CONFIG_POWER_SOURCE:
|
|
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
|
|
return -ENOTSUPP;
|
|
|
|
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
|
|
if (bit < 0) {
|
|
printf("invalid pin %#x", _pin);
|
|
return bit;
|
|
}
|
|
|
|
if (arg != 1800 && arg != 3300)
|
|
return -EINVAL;
|
|
|
|
pocctrl = (void __iomem *)(uintptr_t)addr;
|
|
|
|
val = sh_pfc_read_raw_reg(pocctrl, 32);
|
|
if (arg == 3300)
|
|
val |= BIT(bit);
|
|
else
|
|
val &= ~BIT(bit);
|
|
|
|
if (unlock_reg)
|
|
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
|
|
|
|
sh_pfc_write_raw_reg(pocctrl, 32, val);
|
|
|
|
break;
|
|
|
|
default:
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_pfc_pinconf_pin_set(struct udevice *dev,
|
|
unsigned int pin_selector,
|
|
unsigned int param, unsigned int arg)
|
|
{
|
|
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
|
struct sh_pfc_pinctrl *pmx = &priv->pmx;
|
|
struct sh_pfc *pfc = &priv->pfc;
|
|
const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
|
|
|
|
sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_pfc_pinconf_group_set(struct udevice *dev,
|
|
unsigned int group_selector,
|
|
unsigned int param, unsigned int arg)
|
|
{
|
|
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
|
struct sh_pfc_pinctrl *pmx = &priv->pmx;
|
|
struct sh_pfc *pfc = &priv->pfc;
|
|
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < grp->nr_pins; i++)
|
|
sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct pinctrl_ops sh_pfc_pinctrl_ops = {
|
|
.get_pins_count = sh_pfc_pinctrl_get_pins_count,
|
|
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
|
|
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
|
|
.get_group_name = sh_pfc_pinctrl_get_group_name,
|
|
.get_functions_count = sh_pfc_pinctrl_get_functions_count,
|
|
.get_function_name = sh_pfc_pinctrl_get_function_name,
|
|
|
|
#if CONFIG_IS_ENABLED(PINCONF)
|
|
.pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
|
|
.pinconf_params = sh_pfc_pinconf_params,
|
|
.pinconf_set = sh_pfc_pinconf_pin_set,
|
|
.pinconf_group_set = sh_pfc_pinconf_group_set,
|
|
#endif
|
|
.pinmux_set = sh_pfc_pinctrl_pin_set,
|
|
.pinmux_group_set = sh_pfc_pinctrl_group_set,
|
|
.set_state = pinctrl_generic_set_state,
|
|
|
|
.gpio_request_enable = sh_pfc_gpio_request_enable,
|
|
.gpio_disable_free = sh_pfc_gpio_disable_free,
|
|
};
|
|
|
|
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
|
|
{
|
|
unsigned int i;
|
|
|
|
/* Allocate and initialize the pins and configs arrays. */
|
|
pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
|
|
GFP_KERNEL);
|
|
if (unlikely(!pmx->configs))
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pfc->info->nr_pins; ++i) {
|
|
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
|
|
cfg->type = PINMUX_TYPE_NONE;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
|
{
|
|
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
|
enum sh_pfc_model model = dev_get_driver_data(dev);
|
|
fdt_addr_t base;
|
|
|
|
base = dev_read_addr(dev);
|
|
if (base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
|
|
if (!priv->pfc.regs)
|
|
return -ENOMEM;
|
|
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7790
|
|
if (model == SH_PFC_R8A7790)
|
|
priv->pfc.info = &r8a7790_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
|
if (model == SH_PFC_R8A7791)
|
|
priv->pfc.info = &r8a7791_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7792
|
|
if (model == SH_PFC_R8A7792)
|
|
priv->pfc.info = &r8a7792_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
|
if (model == SH_PFC_R8A7793)
|
|
priv->pfc.info = &r8a7793_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
|
if (model == SH_PFC_R8A7794)
|
|
priv->pfc.info = &r8a7794_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
|
if (model == SH_PFC_R8A7795)
|
|
priv->pfc.info = &r8a7795_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
|
if (model == SH_PFC_R8A7796)
|
|
priv->pfc.info = &r8a7796_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
|
|
if (model == SH_PFC_R8A774A1)
|
|
priv->pfc.info = &r8a774a1_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
|
|
if (model == SH_PFC_R8A774B1)
|
|
priv->pfc.info = &r8a774b1_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
|
if (model == SH_PFC_R8A774E1)
|
|
priv->pfc.info = &r8a774e1_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
|
if (model == SH_PFC_R8A77965)
|
|
priv->pfc.info = &r8a77965_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77970
|
|
if (model == SH_PFC_R8A77970)
|
|
priv->pfc.info = &r8a77970_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77980
|
|
if (model == SH_PFC_R8A77980)
|
|
priv->pfc.info = &r8a77980_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
|
if (model == SH_PFC_R8A77990)
|
|
priv->pfc.info = &r8a77990_pinmux_info;
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77995
|
|
if (model == SH_PFC_R8A77995)
|
|
priv->pfc.info = &r8a77995_pinmux_info;
|
|
#endif
|
|
|
|
priv->pmx.pfc = &priv->pfc;
|
|
sh_pfc_init_ranges(&priv->pfc);
|
|
sh_pfc_map_pins(&priv->pfc, &priv->pmx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7790
|
|
{
|
|
.compatible = "renesas,pfc-r8a7790",
|
|
.data = SH_PFC_R8A7790,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
|
{
|
|
.compatible = "renesas,pfc-r8a7791",
|
|
.data = SH_PFC_R8A7791,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7792
|
|
{
|
|
.compatible = "renesas,pfc-r8a7792",
|
|
.data = SH_PFC_R8A7792,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
|
{
|
|
.compatible = "renesas,pfc-r8a7793",
|
|
.data = SH_PFC_R8A7793,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
|
{
|
|
.compatible = "renesas,pfc-r8a7794",
|
|
.data = SH_PFC_R8A7794,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
|
{
|
|
.compatible = "renesas,pfc-r8a7795",
|
|
.data = SH_PFC_R8A7795,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
|
{
|
|
.compatible = "renesas,pfc-r8a7796",
|
|
.data = SH_PFC_R8A7796,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
|
|
{
|
|
.compatible = "renesas,pfc-r8a774a1",
|
|
.data = SH_PFC_R8A774A1,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
|
|
{
|
|
.compatible = "renesas,pfc-r8a774b1",
|
|
.data = SH_PFC_R8A774B1,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
|
{
|
|
.compatible = "renesas,pfc-r8a774e1",
|
|
.data = SH_PFC_R8A774E1,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
|
{
|
|
.compatible = "renesas,pfc-r8a77965",
|
|
.data = SH_PFC_R8A77965,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77970
|
|
{
|
|
.compatible = "renesas,pfc-r8a77970",
|
|
.data = SH_PFC_R8A77970,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77980
|
|
{
|
|
.compatible = "renesas,pfc-r8a77980",
|
|
.data = SH_PFC_R8A77980,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
|
{
|
|
.compatible = "renesas,pfc-r8a77990",
|
|
.data = SH_PFC_R8A77990,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_PINCTRL_PFC_R8A77995
|
|
{
|
|
.compatible = "renesas,pfc-r8a77995",
|
|
.data = SH_PFC_R8A77995,
|
|
},
|
|
#endif
|
|
{ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(pinctrl_sh_pfc) = {
|
|
.name = "sh_pfc_pinctrl",
|
|
.id = UCLASS_PINCTRL,
|
|
.of_match = sh_pfc_pinctrl_ids,
|
|
.priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
|
|
.ops = &sh_pfc_pinctrl_ops,
|
|
.probe = sh_pfc_pinctrl_probe,
|
|
};
|