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https://github.com/brain-hackers/u-boot-brain
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![Andre Przywara](/assets/img/avatar_default.png)
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
141 lines
4.2 KiB
ArmAsm
141 lines
4.2 KiB
ArmAsm
/*
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* code for switching cores into non-secure state
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*
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* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/armv7.h>
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.arch_extension sec
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/* the vector table for secure state */
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_monitor_vectors:
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.word 0 /* reset */
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.word 0 /* undef */
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adr pc, _secure_monitor
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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/*
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* secure monitor handler
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* U-boot calls this "software interrupt" in start.S
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* This is executed on a "smc" instruction, we use a "smc #0" to switch
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* to non-secure state.
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* We use only r0 and r1 here, due to constraints in the caller.
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*/
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.align 5
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_secure_monitor:
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mrc p15, 0, r1, c1, c1, 0 @ read SCR
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bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
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orr r1, r1, #0x31 @ enable NS, AW, FW bits
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mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
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movs pc, lr @ return to non-secure SVC
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/*
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* Switch a core to non-secure state.
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*
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* 1. initialize the GIC per-core interface
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* 2. allow coprocessor access in non-secure modes
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* 3. switch the cpu mode (by calling "smc #0")
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*
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* Called from smp_pen by secondary cores and directly by the BSP.
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* Do not assume that the stack is available and only use registers
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* r0-r3 and r12.
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*
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* PERIPHBASE is used to get the GIC address. This could be 40 bits long,
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* though, but we check this in C before calling this function.
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*/
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ENTRY(_nonsec_init)
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#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
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ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
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#else
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mrc p15, 4, r2, c15, c0, 0 @ read CBAR
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bfc r2, #0, #15 @ clear reserved bits
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#endif
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add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
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mvn r1, #0 @ all bits to 1
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str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
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mrc p15, 0, r0, c0, c0, 0 @ read MIDR
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ldr r1, =MIDR_PRIMARY_PART_MASK
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and r0, r0, r1 @ mask out variant and revision
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ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
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cmp r0, r1 @ check for Cortex-A7
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ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
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cmpne r0, r1 @ check for Cortex-A15
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movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
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moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
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add r3, r2, r1 @ r3 = GIC CPU i/f addr
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mov r1, #1 @ set GICC_CTLR[enable]
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str r1, [r3, #GICC_CTLR] @ and clear all other bits
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mov r1, #0xff
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str r1, [r3, #GICC_PMR] @ set priority mask register
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movw r1, #0x3fff
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movt r1, #0x0006
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mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
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/* The CNTFRQ register of the generic timer needs to be
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* programmed in secure state. Some primary bootloaders / firmware
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* omit this, so if the frequency is provided in the configuration,
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* we do this here instead.
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* But first check if we have the generic timer.
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*/
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#ifdef CONFIG_SYS_CLK_FREQ
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
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cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
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ldreq r1, =CONFIG_SYS_CLK_FREQ
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mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
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#endif
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adr r1, _monitor_vectors
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mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
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mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
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isb
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smc #0 @ call into MONITOR mode
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mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
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mov r1, #1
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str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
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add r2, r2, #GIC_DIST_OFFSET
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str r1, [r2, #GICD_CTLR] @ allow private interrupts
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mov r0, r3 @ return GICC address
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bx lr
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ENDPROC(_nonsec_init)
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