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https://github.com/brain-hackers/u-boot-brain
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7f79dfb48b
This problem is seen on Zoom1 and Zoom2 in the startup and when i2c probe is used Before : In: serial Out: serial Err: serial timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_pin: I2C_STAT=1000 I2C read: I/O error timed out in wait_for_bb: I2C_STAT=1000 timed out in wait_for_bb: I2C_STAT=1000 Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000 02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip> After : In: serial Out: serial Err: serial Die ID #327c00020000000004013ddd05026013 Hit any key to stop autoboot: 0 OMAP3 Zoom1# i2c probe Valid chip addresses: 48 49 4A 4B The addresses are for the twl4030. The prescalar that converts the function clock to the sampling clock is hardcoded to 0. The reference manual recommends 7 if the function clock is 96MHz. Instead of just changing the hardcoded values, the prescalar is calculated from the value I2C_IP_CLK. The i2c #defines are in kHz. The speed passed into the i2c init routine is in Hz. To be consistent, change the defines to be in Hz. The timing calculations are based on what is done in the linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as apposed to what is done in TRM. The major variables in the timing caculations are specified as #defines that can be overriden as required. The variables and their defaults are I2C_IP_CLK SYSTEM_CLOCK_96 I2C_INTERNAL_SAMPLING_CLK 19200000 I2C_FASTSPEED_SCLL_TRIM 6 I2C_FASTSPEED_SCLH_TRIM 6 I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM This was runtime verified on Zoom1, Zoom2, Beagle and Overo. The 400kHz and 3.4M cases were verifed on test Zoom1, Zoom2, Beagle and Overo configurations. Testing for omap2 will be done in a second step as Nishanth and Jean-Christophe commented. Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Heiko Schocher <hs@denx.de>
152 lines
6.1 KiB
C
152 lines
6.1 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP24XX_I2C_H_
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#define _OMAP24XX_I2C_H_
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#define I2C_BASE 0x48070000
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#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
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#define I2C_REV (I2C_BASE + 0x00)
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#define I2C_IE (I2C_BASE + 0x04)
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#define I2C_STAT (I2C_BASE + 0x08)
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#define I2C_IV (I2C_BASE + 0x0c)
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#define I2C_BUF (I2C_BASE + 0x14)
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#define I2C_CNT (I2C_BASE + 0x18)
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#define I2C_DATA (I2C_BASE + 0x1c)
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#define I2C_SYSC (I2C_BASE + 0x20)
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#define I2C_CON (I2C_BASE + 0x24)
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#define I2C_OA (I2C_BASE + 0x28)
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#define I2C_SA (I2C_BASE + 0x2c)
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#define I2C_PSC (I2C_BASE + 0x30)
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#define I2C_SCLL (I2C_BASE + 0x34)
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#define I2C_SCLH (I2C_BASE + 0x38)
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#define I2C_SYSTEST (I2C_BASE + 0x3c)
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/* I2C masks */
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/* I2C Interrupt Enable Register (I2C_IE): */
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#define I2C_IE_GC_IE (1 << 5)
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#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
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#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
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#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
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#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
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#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C Status Register (I2C_STAT): */
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#define I2C_STAT_SBD (1 << 15) /* Single byte data */
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#define I2C_STAT_BB (1 << 12) /* Bus busy */
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#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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#define I2C_STAT_AAS (1 << 9) /* Address as slave */
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#define I2C_STAT_GC (1 << 5)
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#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
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#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
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#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
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#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
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#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C Interrupt Code Register (I2C_INTCODE): */
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#define I2C_INTCODE_MASK 7
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#define I2C_INTCODE_NONE 0
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#define I2C_INTCODE_AL 1 /* Arbitration lost */
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#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
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#define I2C_INTCODE_ARDY 3 /* Register access ready */
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#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
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#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
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/* I2C Buffer Configuration Register (I2C_BUF): */
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#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
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#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
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/* I2C Configuration Register (I2C_CON): */
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#define I2C_CON_EN (1 << 15) /* I2C module enable */
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#define I2C_CON_BE (1 << 14) /* Big endian mode */
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#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
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#define I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
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#define I2C_CON_XA (1 << 8) /* Expand address */
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#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
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#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
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/* I2C System Test Register (I2C_SYSTEST): */
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#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
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#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */
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#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
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#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
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#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
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#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
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#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
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#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
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/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */
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#define OMAP_I2C_STANDARD 100000
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#define OMAP_I2C_FAST_MODE 400000
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#define OMAP_I2C_HIGH_SPEED 3400000
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#define SYSTEM_CLOCK_12 12000000
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#define SYSTEM_CLOCK_13 13000000
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#define SYSTEM_CLOCK_192 19200000
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#define SYSTEM_CLOCK_96 96000000
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#ifndef I2C_IP_CLK
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#define I2C_IP_CLK SYSTEM_CLOCK_96
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#endif
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#ifndef I2C_INTERNAL_SAMPLING_CLK
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#define I2C_INTERNAL_SAMPLING_CLK 19200000
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#endif
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/* These are the trim values for standard and fast speed */
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#ifndef I2C_FASTSPEED_SCLL_TRIM
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#define I2C_FASTSPEED_SCLL_TRIM 6
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#endif
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#ifndef I2C_FASTSPEED_SCLH_TRIM
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#define I2C_FASTSPEED_SCLH_TRIM 6
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#endif
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/* These are the trim values for high speed */
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#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
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#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
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#endif
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#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
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#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
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#endif
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#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
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#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
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#endif
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#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
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#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
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#endif
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#define I2C_PSC_MAX 0x0f
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#define I2C_PSC_MIN 0x00
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#endif
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